Week In Review: Design, Low Power

ANSYS acquired the assets of DfR Solutions, a developer of automated design reliability analysis software. Founded in 2004 and based in Maryland, DfR’s tool translates ECAD and MCAE data into 3D finite element models, automates thermal derating and performs thermal and mechanical analysis of electronics earlier in the design cycle. “ANSYS brings industry-leading electronic simulation capabilities while DfR’s Sherlock extends the value of simulation by clearly quantifying the real-world cost of design and material selection decisions,” said Craig Hillman, CEO, DfR Solutions. “This acquisition brings the entire design workflow, from functional block to change management, to the customers of both organizations.”

Tools & IP
Synopsys debuted VIP for NVDIMM-P for DDR5/4. Aimed at storage-class memory for enterprise applications, NVDIMM-P is a two-in-one hybrid memory technology with non-volatility and persistence of Flash, and speed, performance, and endurance of DRAM. The VIP uses a native SystemVerilog UVM architecture and includes built-in coverage and verification plans.

Synopsys also launched VESA Display Stream Compression (DSC) Encoder and Decoder IP for visually lossless compression. It interoperates with DesignWare HDMI 2.1, DisplayPort, and MIPI DSI IP and is compliant with VESA DSC 1.1 and 1.2a standards, including providing 120Hz refresh rate and HDR for up to 10K resolutions. A single instance of the IP can be shared across HDMI, DisplayPort, and MIPI DSI interfaces and compressed data can be distributed across up to 16 parallel slices.

eSilicon taped out a 7nm test ASIC that supports 400G gearbox and retimer functionality. The test ASIC includes four lanes of eSilicon’s long-reach 112 Gbps SerDes and eight lanes of its long-reach 56 Gbps SerDes, integrated with media access control (MAC), forward error correction (FEC) and gearbox IP from Precise-ITC.

Pro Design added to its proFPGA FPGA-based Prototyping product family with three new systems based on Intel’s Arria 10 FPGA. Available as three types of motherboards, uno, duo, and quad, the modular system targets small to medium-sized IP and SoC designs and offers a capacity from 8M ASIC gates up to 32M ASIC gates on one system. Up to nine systems can be connected together. By using the Arria 10, the company says it can provide a more cost efficient prototyping system that can be expanded later with high-end FPGAs.

Moortec’s In-Chip Monitoring solution on TSMC 7nm FinFET process is now available as part of Arm’s Neoverse N1 System Development Platform (SDP). The infrastructure-specific system development platform enables asymmetrical compute acceleration through the CCIX interconnect architecture, and the two companies collaborated on a test chip.

VeriSilicon licensed Arteris IP’s FlexNoC interconnect IP as the on-chip communications backbone for use in multiple chips. VeriSilicon cited reduction in development time and the ability to easily implement more complex SoCs.

Synopsys and Arm teamed up on QuickStart Implementation Kits (QIKs) using Synopsys’ Fusion Compiler to improve PPA of designs using current and future Arm processors. QIKs include scripts and reference guides to capture the best practices for implementation, plus take advantage of Arm Artisan Physical IP and POP IP.

Gowin Semiconductor now supports the HyperBus interface specification for their FPGA and programmable SoC products to support external low pin count memories and the PSRAM provided internally. The HyperBus interface consumes 11 pins and additional memories can be multiplexed using an additional chip select.

Numbers & People
Inder M. Singh joined Arm as the company’s new CFO. Previously, Singh served as CFO for Unisys. Prior to Unisys, Singh was managing director, technology, media and communications at SunTrust Bank.

The first quarter of 2019 saw one of the sharpest declines in the IC market compared to the previous quarter, falling 17.6% from Q4 2018, according to market research firm IC Insights. This leads them to forecast a 9% drop for this year.

Additionally, the Semiconductor Industry Association (SIA) and WSTS report worldwide sales of semiconductors fell 15.5% to $96.8 billion in Q1 2019 compared to the last quarter, a drop of 13% compared to Q1 2018.

ANSYS reported financial results for the first quarter of 2019 with revenue of $317.1 million, up 12% from the first quarter last year. On a GAAP basis, earnings per share for Q1 2019 were $1.01, up 3% from $0.98 in Q1 2018. Non-GAAP earnings were $1.29 per share, up 8% from $1.20 per share in the same quarter last year. “Earnings were very strong for the quarter, and our operating margin was above the high end of our guidance, driven by the over-performance in revenues. As a result of our solid performance in Q1, combined with our growing business momentum, we are raising our full-year 2019 guidance,” said ANSYS CFO Maria Shields.

Events
Accellera UVM-AMS PWG Kickoff: May 22 in Munich, Germany. A meeting to assess industry interest in standardizing analog/mixed-signal extensions for UVM. Open to all, but registration is required.

ESD Alliance CEO Outlook: May 23 6:00 p.m. to 8:300 p.m. in Milpitas, CA. This year’s panelists extend across the semiconductor supply chain: John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business. Attendance is free, but registration is required.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.