Week In Review: Design, Low Power

Micron acquired FWDNXT, an AI software and hardware startup. Founded in 2017 and based in Lafayette, Indiana, FWDNXT, specializes in building machine learning deep neural network inference accelerators scalable from edge devices to server-class performance as Xilinx FPGAs, SoCs, or SDK. The company’s engine already powers Micron’s Deep Learning Accelerator (DLA) technology.

“FWDNXT is an architecture designed to create fast-time-to-market edge AI solutions through an extremely easy to use software framework with broad modeling support and flexibility,” said Micron Executive Vice President and Chief Business Officer Sumit Sadana. “FWDNXT’s five generations of machine learning inference engine development and neural network algorithms, combined with Micron’s deep memory expertise, unlocks new power and performance capabilities to enable innovation for the most complex and demanding edge applications.”

Optima Design Automation launched from stealth with a new fault analysis technology platform for safety-critical applications. The Optima Safety Platform includes a range of automated solutions for hard-error (permanent) and soft-error (transient) fault analysis, coverage maximization and structural analysis. Optima said private benchmarks have shown its technology to provide much faster fault analysis compared to traditional fault simulation. The company was founded in 2014 and is headquartered in Nazareth, Israel. Optima received a European Union Horizon 2020 Grant of 2.5 million euro, as well as other financing.

Accellera is forming a Proposed Working Group to focus on a standard to enable tool interoperability between Failure Modes, Effects, and Diagnostic Analysis (FMEDA) for functional safety and the design and verification flow of electronic circuits and systems. “The EDA industry is already developing tools to perform functional safety analysis and this initiative aims at improving interoperability to capture, propagate, and trace the safety intent and optimizations through an EDA solution and across FMEDA tools,” stated Martin Barnasconi, Accellera Technical Committee Chair. “We invite companies active in this domain to share their best practices, requirements, and expectations on what a functional safety standard should encompass.” The first meeting will be held on Dec. 6 at NXP in Munich, Germany. Participants do not need to be from Accellera member companies.

Tools & IP
Synopsys launched DesignWare Die-to-Die PHY IP for ultra- and extra-short reach connectivity in multi-chip modules (MCM) for hyperscale data center, AI, and networking designs. It supports NRZ and PAM-4 signaling from 2.5G to 112G data rates, provides less than 1pJ/bit for optimal energy efficiency, and enables partitioning of the core logic across multiple dies with low-latency and bit error rate.

SiFive uncorked the new U8-Series Core IP and an optimized HBM2E+ solution. Based on the RISC-V ISA, U8-Series Core IP is designed for energy- and area-efficiency and has a superscalar design, featuring a scalable out-of-order pipeline with configurable options for use in real-time or application processors. It has optional floating-point unit, customized instruction extension capability, and RISC-V vector extension support. The HBM2E+ IP offers memory bandwidth up to 400Gbps, or 3.2Gbps per pin, and has been validated in a leading-edge 7nm process technology.

Mentor scaled its analog/RF/mixed-signal (AMS) verification software up to 10,000 cores on the Microsoft Azure cloud platform. Mentor’s library characterization suite and Analog FastSPICE & Eldo circuit simulators were used to characterize standard cell libraries across a broad range of PVT values in the demonstration.

Rambus achieved 18 Gbps data rate with its GDDR6 Memory PHY, which pairs with the companion GDDR6 memory controller from the recent acquisition of Northwest Logic for a complete memory subsystem. It is targeted at high-performance applications including networking, data center, ADAS, machine learning and AI.

Deals
AMD inked a multi-year agreement to use Synopsys’ ZeBu Server 4 emulation system in developing processor, graphics, and gaming chips. AMD cited the ability to efficiently analyze energy efficiency and performance of new architectures. As part of the agreement Synopsys will optimize its ZeBu and VCS software for execution on AMD EPYC processor-based servers, with initial optimization showing a total cost of ownership reduction.

BittWare included Achronix’ 7nm Speedster7t AC7t1500 FPGA in its VectorPath S7t-VG6 accelerator card targeting high-performance compute and data acceleration applications. The card includes 1x400GbE and 2x100GbE ports and 8 banks of GDDR6 memory with aggregate bandwidth of 4Tbps for high-bandwidth data acceleration. The VectorPath accelerator card includes a full suite of Achronix’s ACE development tools along with BittWare’s board management controller and developer toolkit.

NSITEXE used Synopsys’ DesignWare Interface and Foundation IP portfolios in its high-performance Data Flow Processor (DFP)-based SoC, seeing first-pass silicon success on the test chip. IP used included Controller and PHY IP for PCI Express and LPDDR, Embedded Memories and Logic Libraries, and STAR Memory System and STAR Hierarchical System.

Events
Check out upcoming industry events and conferences: The 2019 Phil Kaufman Award will be presented to Mary Jane Irwin on Nov. 7, with a presentation and dinner beginning at 6:30 p.m. in San Jose, California. The ESD Alliance will host a program during SEMICON Europa in Munich, Germany, on November 13 featuring a series of presentations and a panel discussion highlighting how advances in electronic system design are enabling emerging and future applications. Accellera will hold a Proposed Working Group meeting on a potential standard for FMEDA tool interoperability on Dec. 6 at NXP in Munich, Germany. The RISC-V Summit will include talks, an expo, and tutorials on the open ISA Dec. 10-12 in San Jose, CA.