Week In Review: Design, Low Power

Intel buys Habana Labs; HLS optimization; eMRAM test.


Intel acquired Habana Labs, a maker of programmable deep learning accelerators for the data center, for approximately $2 billion. Based in Israel, Habana was founded in 2016 but only emerged from stealth in September 2018 with the release of its first inference chip. Intel’s VC arm, Intel Capital, previously invested in the startup. Intel has made numerous M&A moves in the AI space, including the 2016 acquisitions of Nervana and Movidius and 2017’s $15.3 billion acquisition of Mobileye, and expects to see over $3.5 billion in AI-driven revenue in 2019. Habana will remain an independent business unit and will continue to be led by its current management team.

Tools & IP
Silexica debuted the latest version of SLX FPGA to optimize C/C++ code for HLS in Xilinx’s Vivado and Vitis flows. The latest v19.4 release adds support for arbitrary precision integer data types, improved synthesizability checks and guidance to support C++ specific constructs, a Function Mapping Editor to display a project’s functions and their dependencies, modeling of platform interfaces, and improvements to the time required to analyze user code.

Aldec added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM). In addition, Riviera-PRO’s Register Generator has been enhanced to support FIFOs, indirect registers and arrays of registers.

Codasip released the latest versions of Codasip Studio and CodeSpace 8.2.0. New features include support for Compiler Security Features, C++ applications (LLVM 8.0.0), and RISC-V External Debug Interface.

Mentor will provide an IC test solution for the eMRAM compiler IP from Arm, built on Samsung Foundry’s 28nm FDSOI process technology. The testing solution under development by Mentor and Arm involves the expansion of new Memory BIST hardware and test algorithms to increase memory yield by combining spare resources and multi-bit ECC logic. Samsung is collaborating with Arm on a test chip to leverage actual silicon results to expand the new Memory BIST capabilities.

Pro Design announced a new module for its proFPGA prototyping solution. The Xilinx Virtex UltraScale+ XCVU13P FPGA module focuses on signal integrity and performance with the latest Samtec SEARAY and recently released NOVARAY high-speed connectors. It can reach a point-to-point speed of more than 1.4 Gbps single-ended over the regular FPGA IOs and up to 32.75 Gbps over the GTY transceivers.

Synopsys debuted the latest version of its CODE V optical design software, adding extended CAD model support with flexible options to load CAD surfaces for ray tracing and 3D visualization, new freeform surfaces for compact optical systems, and improvements to the SpecBuilder feature to help track and communicate how well optical system designs meet project specifications and goals.

Alma Technologies uncorked a new Ultra-High Throughput JPEG 2000 encoder IP Core. The UHT-JPEG2K-E IP core implements Part 1 of ISO/IEC 15444-1 image compression standard and supports lossy and lossless encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 video streams, in 8 up to 16 bits sample depths. The encoder is based on a scalable parallel architecture using multiple internal compression engines. It includes AXI4 streaming input and output interfaces.

CEVA added to its Hillcrest Labs sensor fusion product family with the MotionEngine Air software for low power, motion-based gesture control, 3D motion tracking and pointing for consumer handheld devices such as stylus pens, game controllers, remotes, and AR/VR controllers. It can run on a variety of processors, including Arm Cortex-M, RISC-V and CEVA-BX and CEVA-TeakLite families of DSPs.

Wind River’s VxWorks RTOS now supports RISC-V. The VxWorks RTOS was recently updated to support C++17, Boost, Python, and Rust as well as adding a new LLVM-based infrastructure.

Deals & Numbers
ANSYS will join the NASDAQ-100 Index when the stock market opens on Dec. 23, 2019. The NASDAQ-100 index is composed of the 100 largest non-financial company stocks listed on The Nasdaq Stock Market based on market capitalization.

Enflame Technology used Mentor’s Tessent software product family to successfully meet silicon test requirements and achieve rapid test bring-up for its new Deep Thinking Unit (DTU) chip, which targets deep learning training in datacenters. Enflame cited faster DFT development and debugging turnaround cycles between design, verification and physical design, as well as hierarchical DFT capabilities.

Check out upcoming industry events and conferences: Next year, DesignCon will take place January 28-30 in Santa Clara, CA, with a focus on board and high-speed communications design. Plus, DAC submissions for the Designer and IP Track are open through Jan. 22, 2020; the conference will be co-located with SEMICon West July 19-23, 2020 in San Francisco, CA.

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