Week In Review: Design, Low Power

Silicon Labs buys Redpine Signals’ Wi-Fi, Bluetooth biz; unified placement and physical optimization; physically aware RTL design.


Silicon Labs will acquire Redpine Signals’ Wi-Fi and Bluetooth business, development center in Hyderabad, India, and extensive patent portfolio for $308 million in cash. Silicon Labs says the acquisition will expand the company’s IoT wireless technology, including smart phone and industrial IoT, and accelerate its roadmap for Wi-Fi 6. The deal is expected to close in the second quarter of 2020.

Tools & IP
Cadence unveiled the latest release of its digital full flow. New capabilities include a unified placement and physical optimization engines plus machine learning capabilities, which it says provides up to 3X faster throughput and up to 20% improved PPA. It includes integrated timing and voltage-drop (IR drop) signoff engines, for signoff convergence. MediaTek noted it was able to quickly train a model of a CPU core with an improved maximum frequency along with an 80% reduction in total negative slack. Samsung used it to train a model of a design at the 4nm EUV node and improved total power by 6%.

Synopsys launched RTL Architect, a physically aware RTL design system that aims to reduce the SoC implementation cycle in half. It utilizes a rapid multi-objective prediction engine derived from the Synopsys Fusion Design Platform implementation environment to predict PPA of downstream implementation accurately. Renesas is using it to explore and validate various architectures at the RTL stage. Arm is using it to accelerate the RTL development cycle for the next-generation of Arm-based processor cores.

SiFive uncorked SiFive Insight, a trace and debug portfolio for RISC-V. It includes  a C++ cross-platform Nexus 5001 trace decoder for RISC-V compliant with the proposed Nexus Trace Working Group specification and is available for all SiFive RISC-V Core IP product lines offered by Core Designer, the company’s cloud-based tool.

Codasip received a Horizon 2020 funding award from the European Union for development of new RISC-V processors. Codasip will use the funding to expand its processor product line from lower to medium-complexity embedded applications and more complex ones involving multicore and high-performance computing.

Cloud simulation provider OnScale will provide free cloud core-hours to customers working from home during office shutdowns. This targets customers using on-premise computing for OnScale engineering simulation and now lack access to their hardware.

Inomize selected Synopsys’ DesignWare 56G Ethernet PHY IP for its next-generation fully integrated high-performance computing and software-defined radio communications SoC requiring low power and high reliability. Inomize cited the IP’s unique transmitter and receiver architecture for making PPA tradeoffs.

Physical Optics Corporation (POC) is using Ansys SCADE simulation software solutions to develop avionics for U.S. military aircraft. POC noted the ability to streamline model-based software development and lower the risk path to certification.

Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead? Plus, learn why shifting left in a complex design is critical, in Timing Closure At 7/5nm.

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