Week In Review, Manufacturing, Test

Samsung announced initial production of its 3nm process node, which uses a gate-all-around (nanosheet) transistor structure that the company calls Multi-Bridge-Channel FET (MBCFET). The first-generation 3nm process can reduce power consumption by up to 45% compared with a 5nm process, as well as improve performance by 23% and reduce area by 16%, according to the company. The second-generation 3nm process aims to reduce power consumption by up to 50%, improve performance by 30%, and reduce area by 35%.

At this week’s 2022 IEEE International Interconnect Technology Conference (IITC 2022), Imec presented options to “reduce the metal line resistance at tight metal pitches, mitigating the resistance/capacitance (RC) increase of future interconnects using direct metal patterning. For the first time, high aspect ratio (AR=6) processing of ruthenium (Ru) in a semi-damascene fashion is experimentally shown to result in about 40% resistance reduction without sacrificing area. Additional simulations confirm the benefits at circuit level in combination with airgaps as dielectrics. A complementary experimental study shows that the reliability of semi-damascene with airgaps is competitive when compared to dual-damascene with low-k dielectrics.”

Vayyar Imaging will use proteanTecs‘ full-lifecycle analytics in its automotive-grade 4D imaging radar-on-chip.

Intel Foundry Services (IFS) selected Ansys’ multiphysics platform for its new cloud alliance initiative. The goal is an “interinteroperable, cloud-enabled semiconductor design flow that will help enable current and future Intel customers to enhance their productivity.”

Chipping Away at the CHIPS Act
The partisan fight over the CHIPS Act heated up this week. Senate Minority Leader Mitch McConnell continues to push back on moving the legislation forward. He tweeted, “Let me be perfectly clear: there will be no bipartisan USICA as long as Democrats are pursuing a partisan reconciliation bill.”

The Washington Post offered a counter-intuitive take on why the CHIPS Act has stalled: “The real problem was that the bipartisan bill was too popular,” wrote Post columnist David Ignatius. In his take, because it seemed like the act would breeze through, members of Congress added too many other items onto it.

Meanwhile, both American and non-American firms continue to convey a sense of urgency. Taiwan also joined the call for passage, warning that the speed of construction on TSMC’s Arizona fab depends on the subsidies coming through, according to a news report in the Washington Post. “TSMC has already begun their construction in Arizona, basically because of trust. They believe the CHIPS Act will be passed by the Congress,” Ming-Hsin Kung, minister of Taiwan’s National Development Council told the Post.

While the legislation stalls, the Texas Enterprise Fund has given GlobiTech Semiconductor a $15 million grant to build the first new silicon wafer facility in the U.S. in over two decades, according to Mark England, GlobiTech President. The new fab will be located in Sherman, Texas, where GlobiTech already has a manufacturing facility.

Geopolitics
In remarks before the Bureau of Industry and Security on Wednesday, U.S. Secretary of commerce Gina M. Raimondo stated: “Global exports of semiconductors to Russia from all sources have declined by almost 90%.”

Chinese companies Connec Electronic, King Pai Technology, Sinno Electronics, Winninc Electronic and World Jetta Logistics have been blocked from buying American technology, due to sanctions violations, according to the U.S. Department of Commerce.

Academic & Government Partnerships
MediaTek is partnering with Purdue University’s College of Engineering to open the U.S. Midwest’s first semiconductor chip design center, to be housed on Purdue’s campus. “The MediaTek investment confirms Indiana’s emergence as a center of semiconductor technology and Purdue’s Discovery Park District as the state’s premier new economic engine,” said Purdue President Mitch Daniels.

Advantest (Singapore) Pte. Ltd. is partnering with Singapore Polytechnic to establish a Test Engineering Centre to train semiconductor test engineers in the Southeast Asia region. Soh Wai Wah, principal and CEO of Singapore Polytechnic, said, “As semiconductor designs become more complex and market pressures rise, highly skilled semiconductor test engineers will play an increasingly critical role in achieving manufacturing and testing excellence so that their products can meet the advanced computational power and capacity standards to create technological breakthroughs.”

Australia is expanding its semiconductor ecosystem with UNSW Sydney now included in the Semiconductor Sector Service Bureau (S3B) consortium. The consortium also includes Macquarie University, University of Sydney, CSIRO and the Australian National Fabrication Facility.

Quantum networking is getting a boost. Six U.S. government agencies established the Washington Metropolitan Quantum Network Research Consortium, or DC-QNet to “create, demonstrate and operate a quantum network as a regional test bed.” The six agencies are the U.S. Army Combat Capabilities Development Command Army Research Laboratory (DEVCOM ARL), the U.S. Naval Research Laboratory (NRL), the U.S. Naval Observatory (USNO), the National Institute of Standards and Technology (NIST), the National Security Agency/Central Security Service Directorate of Research (NSA/CSS-RES), and the National Aeronautics and Space Administration (NASA).

Laser Breakthrough
In Nature, U.C. Berkeley scientists demonstrated what they call the Berkeley Surface Emitting Lasers (BerkSELs), a long-sought breakthrough in scaling laser size with power. “Increasing both size and power of a single-mode laser has been a challenge in optics since the first laser was built in 1960,” said research team leader Boubacar Kanté, Chenming Hu Associate Professor at Berkeley. “Six decades later, we show that it is possible to achieve both these qualities in a laser. I consider this the most important paper my group has published to date.”

Sustainability
Lam Research released its 2021 Environment, Social and Governance Report. The report showed significant reduction in greenhouse gas emissions and water conservation. It also pointed to an interesting side benefit. Because of the greater efficiencies in etch equipment, clean times via chamber modifications were reduced by up to 50%, and helium usage dropped by as much as 80%.

Business and Startups
Semiconductor Engineering launched a new Business & Startups page. Find the latest chip industry stock chart, monthly detailed startup funding reports (including a deep-dive into China’s startups), profiles of new startups, as well as the latest business news.

Upcoming Events
Find upcoming chip industry events, including:

• SEMICON West/DAC: July 11-14 (San Francisco,CA/Hybrid)
• International Symposium on Failure Analysis and Material Testing- FAMT2022: July 22 (Erlangen, Germany/Hybrid)

Call for papers
IEEE IEDM will be held at the Hilton San Francisco Union Square, Dec. 3-7, 2022. The deadline for submitting papers is July 14th.

Further Reading
June’s Manufacturing, Packaging and Materials newsletter includes these featured stories, along with many blogs and white papers:
• Ways To Address The Materials Crunch
• Variation Making Trouble In Advanced Packages
• High-NA EUV May Be Closer Than It Appears

Semiconductor Engineering’s latest Test, Measurement & Analytics newsletter is here, including a special report on keeping IC packages cool. Other top stories include getting to zero defects in auto ICs, removing barriers for end-to-end analytics, and deep learning in inspection.