What’s Holding Back Aging Simulation?

This time-saver still isn’t a standard step in the verification of IC designs.


Aging simulation supplies information about the long-term behavior before an IC enters into production, providing an important early evaluation of the reliability required by the application and specification.

Re-designs due to reliability issues, and over-design with excessive safety margins, are avoided in this way. In addition, the long-term stability can be demonstrated to the customer. In particular, aging simulation takes into account the influence on integrated field effect transistors of the two degradation mechanisms of hot carrier injection (HCI) and bias temperature instability (BTI).

Despite its usefulness, however, the comprehensive and customized simulation of aging is still relatively rare in practice. Qualification according to a standard such as AEC-Q100 is generally considered sufficient instead, although these tests must be performed on the finished product. Moreover, they yield only pass/fail results and provide limited information concerning reliability. In order to gain such insights at an early design stage, aging simulation should be employed as a standard verification step. But how can this become an established practice?

Figure 1: Aging simulation process

In principle, aging simulation builds upon the simulation-based verification that already must be conducted in the analog design process using appropriate test benches. Typical usage scenarios, called mission profiles, are additionally simulated, generating data on voltages, currents, and sometimes also temperatures for all transistors or a selected subset. Aging models are used to determine the individual changes in the properties of every transistor that arise from these loads. The result is a virtual representation of how the circuit will have aged after a certain period of use, assuming repeated application of the mission profile up to this time.

Then the aged circuit can be simulated and analyzed using the already existing test benches. If it still satisfies the specifications, it can be considered reliable. Otherwise, changes must be made to the design. Although this process appears very helpful, it is rarely required by the users of the ICs — the system integrators and OEMs.

There are three technical factors largely standing in the way of the broad use of aging simulation today: the mission profiles, the aging models and the required analysis time.

The mission profiles define typical usage scenarios based on the application, which are then translated to the levels of systems, circuits and their components. Due to the simulation cost, aging simulation mission profiles are limited to a duration of a few milliseconds. As the desired lifespans are measured in years, the aging simulation assumes that the mission profiles will be executed periodically up to the specified lifespan. For example, if the mission profile takes 10 ms and the target lifespan is 10 years, this corresponds to execution of the scenario 3 x 10<sup>10</sup> times. This figure makes clear that the mission profiles have a major influence on the result of the associated aging simulation. The extent to which the aging simulation is impacted by imprecisions and assumptions made in the definition of mission profiles has not yet been fully studied.

Aging models emulate the degradation of integrated transistors and can be made available by foundries as add-ons to the process design kits (PDKs). Extensive research results are already available concerning models for selected transistors and physical effects, such as HCI and BTI. However, the process has to date been labor-intensive, with little uniformity with regard to precision, complexity and interchangeability. This compounds the difficulty of transitioning from individual aging models for selected transistors to complete PDKs, including consistent support of various design environments. In addition, aging models are currently not always available.

Another reason for the reluctance to include aging simulation is that the time and labor cost of verification is already extensive even without this step, regardless of the specific design environment.

Aside from developments in the area of design support, system integrators and OEMs are also seeing a growing need for reliability information along the value chain, especially in automotive electronics and industrial automation. IC development is no exception here.

So what specific steps are required now to achieve progress in the areas of mission profiles, aging models and analysis cost, and to make aging simulation more effective? With regard to mission profiles, procedures and formats are currently in development to support the consistent representation and application of requirements at specific hierarchy levels.

Various industry players and researcher are currently working on universal approaches to aging models. The goal is to optimize both the models themselves and their integration into simulators so that aging models can be made available broadly and efficiently. Concepts for accelerated simulation processes also must be developed and implemented to reduce the analysis time. Every step along this path improves the usefulness of aging simulation as a practical aspect of IC design verification, transforming it into a tremendously valuable tool for supporting the efficient development and long-term use of ICs and electronic systems in our digitalized world.

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