Yield Impact For Wafer Shape Misregistration-Based Binning For Overlay APC Diagnostic Enhancement

How to improve chip yield and the distribution of wafer chip yield by using shape grouping.


By David Jayez, Kevin Jock, Yue Zhou and Venugopal Govindarajulu of GlobalFoundries, and Zhen Zhang, Fatima Anis, Felipe Tijiwa-Birk and Shivam Agarwal of KLA.

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers.1 This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement.

This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

2. Background
Fundamentally, overlay measurements are the measurement of the relative position of two marks printed on a wafer at two different process layers after certain scanner corrections are applied. A prediction of the overlay errors induced by the process steps can be calculated based on the measured wafer geometry changes. This wafer shape deformation impact to overlay is referred to as shape overlay misregistration.

In 1-D theory, x- and y- displacements are solely dependent on variations of stress and shape in the respective directions. When the x and y displacements are of equal magnitude at a given radius from center of wafer, they are said to be axisymmetric. For the axisymmetric case,2 prediction from 1-D theory has excellent matching with displacement, but for non-axisymmetric case, 1-D theory prediction becomes inaccurate due to the variation in displacement not captured by a singular scalar. To correctly capture the overlay displacement, a 2-D approach is required,3 as outlined in Figure 2.

Figure 1: Vector displacement modelling for axisymmetric stress (left) which shows the physical displacement of the wafer and the prediction of 1-D models as well as the formulae for describing stress in 1-D and the conversion to vector displacements (right).

Figure 2: Vector displacement modelling for non-axisymmetric stress which shows the physical displacement vectors of the wafer as well as how a 1-D model would predict displacements (left), as well as the formulae for describing stress in 2-D and its conversion to vector displacements (right).

3. Measurement Method
The measurement tool used for the shape measurements was KLA-Tencor’s Patterned Wafer Geometry (PWG2) metrology system, a dual sided Fizeau interferometer operating at 635nm wavelength. The tool holds the wafer vertically and simultaneously measures both front and back surface geometry in terms of heights (Zfront(x,y) and Zback(x,y)) for the entire wafer with a lateral resolution of 100 microns. A schematic diagram of the PWG2 operation is shown in Figure 3.

Figure 3: Optical schematic of PWG tool, showing simultaneous front and back measurement of wafer.

Wafer geometry describes the dimensional characteristics of a wafer. A variety of metrics are derived by the tool software (called OASys) from the raw measurement data. Some metrics like nanotopography (NT) are calculated for each surface separately while other metrics such as thickness, flatness etc. are calculated based on both front and back surface data. The shape overlay algorithms such as In Plane Distortion (IPD) and GEN-3 (improved IPD as shown in Figure 2) assumes that the shape distortions present on the back of the wafer will translate to the front of the wafer. As such, the GEN-3 algorithm’s calculation of misregistration on PWG entirely relies on the back surface of the wafer.

4. Grouping Theory
In shape based grouping, all wafers are measured for wafer shape at both reference and current lithography levels (commonly referred to as “Pre” and “Post” layers) in order to track the wafer geometry changes induced by process steps between these two lithography layers. The shape data was processed with GEN-3 overlay algorithms outlined in Figure 2 to identify the shape overlay misregistration vectors. Based on a predefined criterion, wafers with similar shape overlay signature are identified and grouped together. This predefined criterion can take into account scanner alignment and correction models and decides the optimum number of groups.

Once the wafer groups are formed, scanner corrections can be identified for one wafer in each group and the same can be applied to other wafers in the group at a particular lithography layer. Previous work has explored the application of send-ahead grouping, by which wafers are classified by shape before lithography.4 The implementation used in this paper is a variation of this full implementation and shown in Figure 4.

Figure 4: Representative graphic visually describing the grouping methodology. (1) Shape measurement is performed on all wafers. (2) The shape overlay is used to categorize the wafers into shape based groups. (3) Lithography process is then performed on the wafers with scanner corrections being applied at the group level. (4) One wafer from each group is then measured for overlay.

5. Application to Production
A lithography process step with significant center to edge variation in overlay was selected for the application of shape based grouping. Shape measurements were performed on ten lots of 25 wafers at the reference layers for the targeted process step. Three lots of wafers were then processed at lithography and received measurement of all wafers at the subsequent overlay step to determine the correlation between shape and the de-corrected overlay. The wafer level correlation between the de-corrected overlay was very poor, with all three lots having a correlation of less than 0.05 for both the x and y vector component. However, a significant improvement in R2 trend was observed when the correlation was plotted radially, as shown in Figure 5.

Figure 5: Correlation between misregistration and decorrected overlay plotted by radius of measurement which shows that the shape prediction to on-product overlay is strongly correlated at wafer edge.

The three correlation lots were then grouped based on within-wafer vector cluster distances – the resultant three groups having distinct signatures, the centroid wafer from each group shown in Figure 6.

Figure 6: Centroid wafers from each identified group for GEN-3 processed shape information from 75 wafers showing the radial signature.

It is expected that the number of groups will increase with the number of lots used for grouping. Also, group signatures are expected to change with time. The cost of implementation is proportional to the number of groups since there is a need to maintain separate scanner corrections for each group. The optimal number of different shape signatures was evaluated based on the seven additional time-separated lots, and we found the number three to be reasonable from an implementation cost point of view, with group signatures shown in Figure 7. The similarity between group signatures based on time separated group of lots shows good persistence for the identified groups in a full manufacturing environment and allows for effective scanner corrections to be applied.

Figure 7: Centroid wafers of groups in control and test lots show good visual correlation especially at edges.

Wafers from each of the seven lots were then split into groups prior to processing at the lithography step being evaluated. This was done to make internally consistent scanner corrections for these lots. After processing, one wafer from each group from each lot was measured at overlay to ensure that there was no adverse shift in process control.

6. Results
All of the correlation lots and the signature grouped lots were processed to end of line and tested electrically for functionality. The signature grouped wafers were compared to equivalent non-grouped wafers, with all other known experimental and line process factors removed. The wafer level yield was divided into five zones with equal numbers of chips, and the outer-most zone was compared between the otherwise equivalent grouped and non-grouped wafers, as shown in Figure 8. The grouped wafers showed an improved chip yield of 1.4% as compared to the baseline non-grouped wafers. Additionally, the grouped wafers show a 20% reduction in distribution, resulting in fewer trailing outliers.

Figure 8: Wafer electrical sort data from wafers which were split into up to three groups based on shape data which shows a 1.4% improvement in yield and a 20% reduction in distribution of yield.

7. Conclusions
In this investigation, we used 75 wafers to prove a radial correlation between wafer shape measured before process at lithography and raw de-corrected overlay measured after lithography and to establish wafer shape groups for all measured wafers prior to lithography. Then, an additional 175 wafers of otherwise full production wafers were measured and grouped based on their shape signature prior to lithography.

The first conclusion to be made is that there is a significant link between the radial stress profile and edge overlay residuals. Moving beyond mean wafer control, the identification and control of edge specific metrics becomes critical for improving functional yield at the edge. The capability and value of radial shape as measured by the PWG tool and its correlation to de-corrected overlay was introduced. Wafer groups based on the shape signatures were then established.

Furthermore, the application of the grouping methodology was applied to 175 full production wafers in a manufacturing setting. By comparing the radial yield at the edge for wafers which were split into shape-representative groups, a significant improvement was observed in both the wafer mean chip yield as well as the distribution of wafer chip yield. This confirms that the shape grouping methodology is capable of considerable positive impact on real world line variability.

[1] Peterson, J., Rusk, G., Veeraraghavan, S., Huang, K., Koffas, T., Kimani, P., & Sinha, J., “Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes,” Proc. SPIE 9424, 94240N (2015).
[2] Brunner, T. A., Menon, V. C., Wong, C. W., Gluschenkov, O., Belyansky, M. P., Felix, N. M., Ausschnitt, C. P., Vukkadala, P., Veeraraghavan, S., and Sinha, J. K., “Characterization of Wafer Geometry and Overlay Error on Silicon Wafers with Nonuniform Stress,” Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), 12(4) 043002 (2013).
[3] Reddy, J. N., [Theory and Analysis of Elastic Plates and Shells, 2nd Edition], CRC Press (2007).
[4] Lee, H., Han, S., Woo, J., Park, J., Song, C., Anis, F., Vukkadala, P., Jeon, S., Choi, D.S, Huang, K., Heo, H., Smith, M. D., Robinson, J. C., “Patterned wafer geometry grouping for improved overlay control,” Proc. SPIE 10145, 101450O (2017).

This article was originally published in Proc. SPIE 10585, Metrology, Inspection, and Process Control for Microlithography XXXII, 105851B (2018); doi: 10.1117/12.2302973

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