Balancing Performance And Energy Consumption For IoT Applications Processors

Why processor selection and configuration are so critical.

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Processor requirements in IoT applications continue to grow to support more human interaction. Functions such as detecting speech and faces or delivering a voice message are being added to existing tasks the processors already perform such as system communication and control. Since these applications operate from batteries with defined size and life expectations, not only is the energy consumption budget not growing, but it’s getting smaller as energy harvesting or smaller batteries are considered.

System architects face difficult challenges to meet these increasing requirements. The right processor and the ability to configure it can enable them to address these seemingly conflicting goals.

Combine DSP + RISC processing

IoT devices are defined by their ability to take in or “sense” real world signals, perform operations on the associated data and communicate results over a network, whether it is the internet or a local network. Most general-purpose RISC processors can process the signals successfully, but dedicated DSPs can perform these tasks with better power efficiency and lower latency. On the other hand, RISC processors are well suited for transferring data and setting up communication channels. Using separate independent processors is an option but adds cost and board space to the system as well as the requirement for multiple development and debug environments and tools. This complexity and cost can be reduced using a single processor with both functions.

Key features such as voice triggering, voice control, speech playback, and inertial sensor processing that are needed in always-on and low-power environments leverage DSP instructions to perform tasks such as filtering, Fast Fourier Transform (FFT), and interpolation while still meeting energy goals.

The DesignWare ARC EMxD family of processors meets these challenges by adding a DSP engine with ARCv2DSP instruction set architecture (ISA) to ARC configurable processors to enable RISC and digital signal processing within a single unified architecture (Figure 1). They offer low power consumption and can perform speech detection for voice control in less than 1 µW.

The ARC EM DSP processors are highly configurable so that each instance can be tailored to achieve the optimum balance of DSP and RISC performance for the target application, as well as power- and area-efficiency. For example, the ARC EM5D and EM7D are well suited for applications requiring around 50% DSP processing and the EM9D and EM11D, with support for XY memory, are ideal for more DSP intensive applications.

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Figure 1. The DesignWare ARC EMxD family of processors

Include support for multibank memories

Code used to implement a typical DSP MAC operation in a RISC + DSP processor consists of loading data from memory, followed by performing a MAC operation on the operands. The addition of multibank memories can increase throughput from 1/3 MAC-operations per cycle to 1 MAC per cycle.

An XY-memory system also reduces code size, as there is no need for separate load and increment instructions.

Aside from increased throughput and code size reduction, an often overlooked advantage is lower energy consumption. Energy efficiency for DSP functions can improve significantly with the use of XY memory, as fewer clock cycles are needed for the same functions, especially when they are tailored to a RISC + DSP architecture that allows concurrent accesses for both RISC and DSP.

DMA

Another option to reduce power in a processor system is to use direct memory access (DMA), which enables the peripherals to move data without involvement of the CPU. To ensure an area-efficient system, DMA has to be highly optimized for the processor and application.

Synopsys’ µDMA option for ARC EM processors is designed with IoT applications in mind, and includes only the features needed for this type of embedded system. The µDMA controller enables lower power operation by offering the option to put the EM core to sleep while the µDMA moves data around the chip from peripheral to memory or memory to memory, only waking up the core when it’s needed. Multiple sleep modes allow customization for the lowest possible power.

Accelerate software algorithms

ARC EM processors use ARC Processor EXtension (APEX) technology to allow SoC designers to simplify and automate the process of designing and verifying extensions for common functions like cryptographic software algorithms, or customer-specific code so that these frequently used algorithms take less time, memory, and energy to execute.

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Figure 2. Energy and cycle count reduction running sensor application software with APEX acceleration

When designing a chip for IoT applications, designers often have concerns about trading off energy consumption for performance to meet ever-evolving feature requirements. Designers can make architectural choices that deliver the performance required without sacrificing energy efficiency. Flexibility and configurability are key factors when selecting processor architecture, along with the ability to scale to meet the needs of evolving applications.

The ARC EM family of processors offers scalability and options that can future-proof the product roadmap with the flexibility needed to find an optimum performance to power ratio. With the ability to customize your processor with APEX technology you will also be able to differentiate your product in the competitive IoT market.