A formal age; more finFET layout; TSMC ramps up; 3-D printing; thermal resistances; RISC-V; UVM end-of-test; ARMv8-M security extensions; UHD and HDR; ransomed hospitals; Easter eggs; e templates.
Are we in a new wave of formal? Mentor’s Joe Hupcey III highlights several things from DVCon that indicate formal is becoming a cornerstone of mainstream verification flows.
Synopsys’ Graham Etchells continues his search for more ways to bring greater efficiency to the FinFET layout process, and the downsides to custom routing solutions.
Cadence’s Paul McLellan takes a look at TSMC’s rapid rate of process development and ramping up multiple fabs into high-volume manufacturing.
From homemade braces to a 260 square-foot system for printing electronic circuits, it’s all about 3-D printing in this week’s top five picks from Ansys’ Bill Vandermark.
NXP’s Christopher Hill investigates thermal resistances and whether adding more heatsinking to a MOSFET could assist the die thermal energy in its passage towards ambient.
Rambus’ Aharon Etengoff checks out some recent developments around the RISC-V open source instruction set architecture, including support from a tool kit for building secure special-purpose operating systems.
Verification expert Tudor Timi presents an overview of end-of-test handling in UVM and the different ways of implementing it.
ARM’s Tejas Belagod provides a guide to security extensions and privilege levels in the ARMv8-M architecture.
Samsung’s Dale Stolitzka discusses combining ultra-high definition with high-dynamic range and the latest VESA compression standard.
Semico’s Tony Massimini has fun at the first Silicon Valley ComicCon.
Synopsys’ Robert Vamosi considers the latest problem for hospitals: the rapid growth of targeted ransomware.
Mentor’s John McMillan goes hunting for Easter eggs, and ends up with a basket full of clever doodles hidden in PCBs and chips.
Cadence’s Efrat Shneydor digs into e templates and extending an entire template’s definition.
Plus, check out the blogs featured in last week’s System-Level Design newsletter:
Editor in Chief Ed Sperling contends that the repositioning of the semiconductor industry has finally begun.
Technology Editor Brian Bailey points to a growing divide between the design team, which is stuck using old technology, and rapidly advancing verification technologies.
Cadence’s Frank Schirrmeister observes that it’s still too early to tell if changes underway in the IoT age are positive or negative.
Aldec’s Jacek Majkowski provides a hardware emulation guide for non-C designers.
Mentor Graphics’ Alex Grange and PTC’s Linda Mazzitelli examine the trouble that poor communication can cause.
NetSpeed Systems’ Sundari Mitra argues that engineering schools need to revamp their curricula to address real-world problems.
Synopsys’ Tom De Schutter looks at best practices in FPGA-based prototyping from experts at NVIDIA, Intel, Synopsys, SanDisk and Cisco.
eSilicon’s Mike Gianfagna finds high-school kids building autonomous systems using 3D printers.
OneSpin’s Dave Kelf points to a new, unbiased site for formal verification technology.
Arteris’ Kurt Shuler digs into what you don’t know about getting SoC projects to market.