High-level synthesis market heats up as complexity and early tradeoffs become more difficult.
Cadence agreed to buy Forte Design Systems for an undisclosed sum, enhancing its footprint in the high-level synthesis market as higher levels of abstraction gain traction across the SoC world.
For the better part of a decade high-level synthesis (HLS) has been a market opportunity that was just around the next bend, along with electronic system-level design and SystemC modeling. Mentor Graphics (Vista, CatapultC) and Synopsys (CoWare, Synfora) were the first to recognize the opportunity, followed by Cadence with the introduction of C-to-Silicon. Until recently, the market for HLS has been relatively quiet. In 2013 the market dynamics began changing rather dramatically, as chipmakers began bringing in more third-party IP and mixing it with their own internally developed IP as a way to speed time to market for complex SoCs.
“For a number of years this market has been in the early adoption phase,” said Craig Cochran, vice president of corporate marketing at Cadence. “Customers used it to complement the RTL design work that was being done, with an emphasis on algorithmic technology—particularly audio and video—and then integrating that with the rest of the design. Companies then broadened the scope of the design use for HLS, which in turn fueled its growth. It’s not just about the data path anymore. It’s also about transaction-level modeling and moving verification and synthesis to a higher level of abstraction, not just the RT level.”
Pushing to a higher level of abstraction is vital in designs where there are hundreds of millions of gates, complex power issues to resolve, and the need for quick exploration about what IP will function best where. HLS can also enable multiple micro-architectures for blocks to be explored, often finding solutions that are more optimal than hand coded RTL. The key is to make quick comparisons, figure out what works best, then drill down into the details.
“The key benefit is to bring everything up to the SystemC level and make tradeoffs at a higher level,” said Cochran. “This can provide huge gains in power and allow you to trade that off against performance. It’s also a much more variable way to implement a design, and it has benefits for area, as well.”
The entire modeling market has been witnessing growth for just these reasons. “This is a validation of the importance of having accurate models when it comes to synthesis and in tying them to a virtual prototype,” said Bill Neifert, chief technology officer at Carbon Design Systems.
How exactly Cadence will utilize this technology and its newly minted role in the IP business, based upon a series of acquisitions over the past couple of years, bears watching. It also will be interesting to see how the company merges this with its existing high-level synthesis solution, C-to-Silicon.
All of the Big Three EDA vendors are in a race to couple IP with high-level tools, software, as well as simulation, emulation and increasingly formal verification—and raising questions about who will be in competition with whom and in which markets.
—Ed Sperling and Brian Bailey contributed to this report.