New Challenges Emerge With FinFETs

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More restrictive design rules help diffuse some problems, but the list is extensive and processes are still not fully baked.

Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult.

Early reports back from companies experimenting with finFETs range from business as usual to so difficult that some designs are being rolled back to 20nm without finFETs. Even though double patterning was introduced at 20nm, there isn’t as much needed as at 16/14nm.

“At 16/14nm, a lot of people already are reporting trouble,” said Christen Decoin, product marketing manager for new and emerging markets for Calibre Design Solutions at Mentor Graphics. “For power, there are more issues related to low Vt-high Vt. Double patterning is more prevalent, and metal layers will be a huge problem. At 10nm, the metal is so small that even a tiny electromigration issue will destroy a chip. At 10nm the biggest issue is going to be metallization.”

And because the 16/14nm process is so difficult, designs are being highly constrained. Industry sources say there is about an 80% utilization of SoCs at 28nm, but that number drops to below 60% at 16/14nm. Numbers are improving as the process matures, but it still has a long way to go.

“The problem you run into at 14nm is a finer metal pitch,” said Giorgio Cesana, marketing director at STMicroelectronics. “The transistor integration remains relatively simple, but you do have double patterning for more of the chip.”

About face
There are few secrets here, and word from the front lines of finFET design has flowed freely backward. It’s complex work and it takes more than one company to successfully build an SoC. In fact, it takes an entire ecosystem, and that ecosystem needs to be fully informed to be effective.

“There are three elements coming together,” said Ron Moore, vice president of marketing for the physical IP division at ARM. “The first is that it’s more expensive to do the next chip. The second is that there is uncertainty about demand so companies are looking to get more out of 40nm or 28nm. They’re pushing for one more design at existing technology nodes than what they normally would feel comfortable doing. And the third is that it’s taking longer to bring complex systems to market than in the past, so they’re doing derivative chips at 28nm while moving to 16nm.”

Industry sources say some chipmakers even are backing off 16/14nm for their next chips, choosing instead more limited power/performance benefits at 20nm. There is still double patterning, although for fewer layers, but there is less concern about electromigration and complex thermal issues within densely packed finFETs.

More IP uncertainty
One part of the development process that is emerging as a potential solution—or a potential liability—involves third-party IP and software. Because these designs are so complex, more third-party IP is required. But there is so little contextual history for working at these process nodes that it’s hard to predict what can go wrong.

“Not all IP may be tested as comprehensively as it could be, but more concerning is that the acceptable usage of a complex IP may not be, and possibly cannot be, absolutely defined,” said Bernard Murphy, chief technology officer at Atrenta. “For the IP developer, there is an implicit ‘reasonable” usage.’ But as an IP user, my implicit understanding of ‘reasonable’ may not fully match yours, especially if I am not an expert in that application. Therefore there is potential for use outside design and test expectations. IP suppliers try to forestall this through assertions and comprehensive documentation, but practicality only allows covering most common misuses and misunderstandings.”

This problem is much worse at 14/16nm, where there are more rules and far less wiggle room in designs. Murphy said one solution is for IP suppliers to provide auto-generated assertions embedded in the IP design, which can be triggered if something goes wrong.

“The challenge is that there is no one solution that suits everyone,” said Lawrence Loh, vice president of engineering at Jasper Design Automation. “We have two customers that have taken very different routes. One, which has its own fab, stresses process and relies less on design IP. The other is fabless and develops a lot of their own IP, so they focus on low power and how the IP is integrated. The tradeoff is that each targets their advantages in certain areas.”

That strategy works well enough at mainstream process nodes. But moving it to 16/14nm with finFETs means more rules on every front, including what IP gets certified for manufacturability and the power characteristics for that IP. It also means more uncertainty about how IP will interact with other IP in an untested environment.

“Relying on the data sheet is no longer practical,” said Abhishek Ranjan, engineering manager at Calypto Design. “You need a whole new set of tools to ease optimization for power and help qualification of IP. It doesn’t look like the tools need to change for finFETs, but there’s actually a big change in the way the tools have to work. You understand area versus timing, but you don’t know about the power.”

Cadence’s solution is more configurable IP, which it acquired with Tensilica. Synopsys, meanwhile, has begun introducing more versions of IP that can play nicely in different scenarios. But really understanding the tradeoffs of any of these IP solutions will take time because the processes will continue to shift to improve manufacturability and ultimately to lower the cost. And until that happens, the move to the most advanced process nodes will be fraught with risk, potential opportunity, and lots more second guessing than anytime in the past.




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