Constraints Ubiquity: Impact On Managing Design Closure?

Successful design closure requires that the timing intent as specified by the design constraints matches the functional intent as specified in the design.


By Mark Baker and Ravindra Aneja
Maintaining completeness, correctness and consistency of design constraints is a challenge that is pervasive in the design flow. Multiple transformations, or touch points (as illustrated in the diagram below), exist during the design implementation stages. Additionally, there are parallel stages involving IP development and handoff resulting in SoC integration and design signoff. It’s reasonable to further segment the implementation flow by “Initial Timing Closure” and “Signoff Timing Closure.” This transition reflects the final analysis, in presence of physical effects required to ensure the timing intent specified in the design constraints matches the functional intent as specified in the design.

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Achieving design closure requires effective management of the constraints generation, validation and verification processes. Starting with initial, validated constraints, you can drive the RTL signoff analysis stage. For example, CDC analysis can use SDC constraints to extract clock relationships, extract clock domain information for primary inputs/outputs, extract other input constraints, and to verify exceptions in the design. This ensures RTL signoff analysis and timing analysis are being driven by the same set of constraints. This makes the RTL signoff analysis less error prone and also adds significant productivity to the entire timing analysis process.

As timing analysis evolves, the goal is to identify problems that may not be immediately obvious. Examples include:

  • Generating architectural exceptions that will reduce STA effort
  • Identifying constraints affecting a path that is violating timing
  • Identifying exceptions that correspond to paths not meeting timing

There is also consideration for power and the impact design constraints have on power consumption. If all the clock relationships (i.e. asynchronous, exclusivity, etc.) are not properly defined or if missing timing exceptions exist, the result is extraneous power consumption on the chip.

Managing the impact of constraints ubiquity can be a significant challenge for design teams. The ability to effectively manage the constraints creation, validation and verification process at each stage in the implementation flow is critical to successful design closure.

—Ravindra Aneja is senior technical marketing manager at Atrenta.