Getting to 16nm finFETs has some surprises, a surprising melding of minds in standards and Synopsys surprises during their first acquisition.
The schedule for today revolves around eating and it is perfectly balanced between the big three. The morning starts with breakfast for the Cadence panel titled “Crossing the Great Divide: How to Safely Navigate the move from 28nm to 16FF+.”
The panel was moderated by Brian Fuller and panelists included Jayanta Lahiri from ARM, Afshin Montaz from Broadcom, Scott McCormack from Freescale, Yanqiu Daniel Diao from HiSilicon, Willy Chen from TSMC and Chin-Chi Teng from Cadence.
The panelists talked about some of the difficulties they encountered when they attempted their first 16nm finFET design. But it was not all bad. “The performance was absolutely rocking,” reported ARM’s Lahiri. Broadcom’s Montaz discussed the tradeoffs and concluded that “16nm is not for everyone.” He was surprisingly positive about analog at 16nm and called it “a better process compared to 28nm.”
The panelists talked about the amount of resources necessary, including human and compute resources. “It was not linear,” said McCormack. “We had to upgrade our farm,” added Lahiri. Another common factor was the importance of a three way partnership between designers, fab and EDA.
After conducting another roundtable there was an IP track session on the subject of IP verification. Anne Cirkel, the DAC chair, had been correct in stating that the designer and IP tracks were packed to the gills. The first paper was on the subject of testbench qualification. The main point was that if you inject a bug in the design and it does not lead to a failure in verification, then you have more work to do on the testbench. The difficulty is how many and what types of faults to inject to get the desired confidence in the testbench.
The second paper discussed the verification of DDR memory interfaces and interposer test fixtures. This discussed some of the problems associated with very high-speed interfaces where electrical effects can affect functionality. Paper three was on the subject of testbenches and asked the question why they should control processor execution and the last paper was on the subject of IP-MAP tool for design verification and validation.
After three papers, there was a short panel session that addressed issues such as the verification productivity increases enabled by verification IP and the changing role of engineers within the verification flow. That panel was moderated by Semiconductor Engineering and will be reported in full.
Lunch was a joint affair between Mentor and ANSYS who recently announced the Veloce Power Application that adds an API called Dynamic Read Waveform (DRW) between the two companies’ tools and enables power analysis to be performed on full chip as the OS boots. On the ANSYS side they call this interface PAVES. The speedups are in the order of a 2X to 4X compared to the traditional file based flow. They believe that this speed increase is enough to enable a change in methodology.
The afternoon was a first in that three standards bodies came together to provide a unified voice on the subject of system-level power. The IEEE DASC, Si2 and Accellera made presentation about the work each of them have in progress along with customer presentation about their needs and desires for power standards. One of the goals is to put an end to the power standards war that have been going on for a number of years. Needs presentations came from Microsoft, Xilinx, Barry Pangrle a power consultant and TSMC.
This was followed by short presentations about each of the standards efforts and how they relate to each other. The fact that three independent groups had been established within the IEEE for power was troubling, but Stan Krolikoski was assigned the task of coordination between them. He reported that it had taken a lot of time and effort to bring about the alignment that they believe they have achieved and hopefully put in place a framework to ensure cooperative work in the future.
Poster sessions on the floor appear to be attracting a significant number of people from the academic side of the conference and hopefully once on the floor they will explore a little to see what the industry is doing with the technology they develop. We need to attract and retain people in the industry and the best way is for them to see the types of challenges that EDA engineers deal with every day.
As the day winds down, it again becomes time to think about eating, and this evening will be spent with Synopsys. Over dinner, Chi-Foon Chan the Synopsys co-CEO, was reminded about his first acquisition and the remarkable story of the bus sent to pick up new employees from Zycad. There were many laughs and open jaws at some of the now comic situations associated with that.