Adding both into emulation solves the problem of interaction between real blocks.
In my earlier blogs we’ve heard from some of the experts on using UPF in the successive refinement flow. We’ve talked about controlling leakage power, bringing power down, and validating power management behavior using coverage and simulation, including debug and clock domain crossing verification.
In order to do the last step in the successive refinement flow, you need to use emulation because of the need to run real software and have real blocks interacting together, which is often too much to handle in simulation.
I’m fortunate to have my colleague, Vijay Chobisa, product marketing manager for Mentor Graphics’ Emulation Division, to identify the most significant ways that emulation can help you with power management verification and power analysis. Vijay is a leading expert in low power emulation, having authored and presented several papers and articles based on his many years working with customers to come up with the most useful low power solutions for system level design.
Q: Vijay, my understanding is that with emulation you’re looking at average power, peak power, and verification of power management. Is that correct?
Chobisa: That is. In fact, to cover all of these aspects of power management and power analysis (including time-based power analysis combining emulation with fully integrated power analysis tools), we recently introduced the Veloce Power App.
We all know how important power is for our customers, and power has two aspects: power analysis and power management. Power analysis should tell you how much power your chip is going to consume on average and where its power hotspots are. Power management is all about how you can power down and power up certain functionality without impacting the rest of the operation.
It is very important that you can take your chip through the power down and up sequences just as it would behave in real world scenarios. Only this way can you verify that you are not letting any bugs escape that were introduced by low power management techniques.
Q: What does the UPF flow look like in emulation, and why do you need to do emulation in addition to simulation for verifying the power management?
Chobisa: Typically, low power management verification starts very early on using simulation at the block or IP level, where you make sure that the IP of the design is able to go through the power sequences. Once you’ve put together the entire chip, it is very important that you verify both software and hardware together because that’s how your chip is going to get used in the real-world environment. This software-driven environment is targeted at the SoC level, and you need emulation for that.
To make sure that we are consistent in what we are verifying, emulation complements what you have done in simulation. It supports the same UPF constructs, the same coverage and assertion technologies, and the same debug techniques as simulation with Questa. That way, when you are moving your blocks and your IP from simulation to emulation, you are able to reuse the work you have done in simulation and extend your verification to exercise any holes you want to cover.
Q: So in order to run embedded software, to run stuff this big, you need to see all these interactions and the interactions with the embedded software. Can you give an example of some things your customers have found in emulation that wasn’t found in simulation?
Chobisa: Several customers are using emulation to target how their memories are behaving and figuring out how they can save power. Memories are a big component of the power consumption in SoCs. I can’t stress enough that you really need to be able to have the full system together in order to verify that memories are powering up and down correctly, not corrupting data stored within them in light sleep mode, and not corrupting downstream logic.
Q: What are users looking for in power analysis? Why is it important that you can capture the kind of activity you can when running emulation?
Chobisa: Typically, what people do for power analysis is take a set of adapted vectors and run them over a very small number of cycles on the chip. Based on the power numbers generated, they use some extrapolation technique to come up with the power numbers for the SoC. However, in the last two to three years we have had several customers tell us that the power numbers generated by these adapted vectors were way off compared to the actual power measurements taken when they put the chip in the lab.
Veloce eliminates this problem by putting the entire SoC inside the box, booting the operating system, and running live applications in the same way the chip is going to get used in the real world, so you can see what is really going on. The Veloce Power App allows you to very quickly identify windows of power concern. Once you identify those, you can generate detailed switching activity for those regions and use a power analysis tool to understand how much average power and how much peak power you are actually consuming. This power number is very close to the number you will get when you put the chip on the PCB and measure the power number in lab.
Q: I know that power analysis tools can’t handle the huge volume that’s coming out of emulation, so that’s a huge breakthrough. Veloce runs the entire, real application and then picks which areas are critical. So your power analysis tool doesn’t choke and you can focus your analysis where it is most needed and meaningful.
Chobisa: If you run this kind of test in simulation or without an activity plot, the amount of information generated is ridiculous. No one will be able to handle that. So by identifying hot spots and by running the real application, we are able to accelerate time to accurate power analysis. Veloce’s integration with power analysis tools delivers those accurate numbers very quickly, shortening what we call the “time to power.”
That sounds like the perfect marriage of accuracy and speed. In my next blog, we’ll look deeper into this relationship from the power analysis tool perspective. To learn more about the Veloce Power Apps, check out the new paper Power — Usage Shift Leads to Methodology Shift.