With design requirements of today’s SoCs going beyond performance and area, there are a number of trends where power is concerned.
Given that design requirements for today’s SoCs go well beyond performance and area, energy efficiency and its impact on system design plays a major role for many end applications ranging from wireless sensor networks to autonomous vehicles as well as emerging applications in the Internet of Things market segment, where cooling capability is limited and expensive.
For these reasons, a comprehensive power analysis methodology from system to RTL to gate is crucial for a successful system design. “Generally, the further the design flow is advanced, the greater is the certainty for reaching a valid solution,” according to Vic Kulkarni, senior vice president and general manager at Apache Design. “However, the cost of making power decisions at a lower level of design abstraction is very high. We see a distinct trend where power management decisions must be made at a system level to achieve success.”
He said that historically, system designers used complex spreadsheets to calculate power consumption scenarios for different architectures, but there are major drawbacks for such an approach like limited reuse, cumbersome sharing across teams, error-prone formula management, and no dynamic simulation results to debug power management and directly comparing to measurements.
“System architects have reported that on the electronic system level power saving potentials between 40% to 70% can be expected, 10% to 25% on the RTL, and smaller than 10% on the gate level,” Kulkarni said. ““In order to achieve these objectives at a system level, efficient modeling mechanisms must be in place where lower level power data must be fed into higher level function calls. Si2 has suggested an approach where foundation energy and power data can be stored within such a high level model and then accessed at a pin, bus, RTL, TLM and software levels of abstraction. The architectures and interfaces could be built on top of Liberty models.” He referred to the Si2 patent application from July 2013. The industry has started to collaborate on standardization of these concepts through the Si2 proposed “Multi-Level Power Model.”
From his perspective, the key benefits of such a model (or a variant thereof) will be huge for system architects who will see new power optimization opportunities and have a better QoR with better predictability and reduced number of design architecture iterations.
Along these lines, Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence, observed that users are attaching more meaningful power information to transaction-level models, and introducing more power states. “This specifically allows more efficient development of software controlling the different power states in a design. It also allows them to efficiently analyze and optimize the impact of how memories are accessed, including optimization of cache and software memory access strategies.”
Further, he said, the accuracy of annotated models to higher-levels of abstraction bears accuracy limitations. “As a result, similar to the assessment of performance effects in interconnect, there is a trend to utilize RTL more efficiently. Specifically, users generate more toggle data and longer sequences taking into account software in a more representative way using hardware assisted methods like emulation.”
Of course, low power SoC design is a system design challenge that does not stop at the border between hardware and software, noted Tom De Schutter, senior product marketing manager for Virtualizer Solutions at Synopsys. “The architect, hardware designer, and software developer all play important roles in setting realistic power budgets and achieving the right result for the system.”
Enabling a system to perform with power efficiency requires the right SoC architecture and perfectly matching power management software, he continued. “Architects and software developers need to address this need as early as possible in the development cycle, and system-level tools and methods for virtual prototyping are available today to help them accomplish this. With virtual prototyping, realistic system simulation enables them to define the power budgets and power modes for all primary system components and to bring-up the power management infrastructure needed by the rest of the hardware and software team before the availability of RTL or hardware. This ensures that the final design can take these power optimizations (both hardware and software) into account. Power efficiency has become too important to wait until late in the design cycle to actually measure the power-performance trade-offs.”
Considerations include the following, De Schutter noted:
Top architecture design trends for power
Use of virtual prototypes to:
Top software development trends for power
Use of virtual prototypes to:
Just as design abstraction needs to move to a higher level, so does power abstraction, agreed Anand Iyer, director of product marketing at Calypto. “Migration of power abstraction to system level is perhaps easier than the design abstraction migration. This is because power is a global variable and higher abstraction offers better control. In fact, low-power techniques that are saving maximum power need to be done at system level. Techniques like power gating and dynamic voltage and frequency scaling (DVFS) are more effective at the system level than at the block level. We do see the trend of designers wanting more formal specification of power requirements at the system level. The specification should be implementation-agnostic and thereby enable the designers to explore multiple implementations within a given power envelope.”
He pointed out that one of the obstacles to raising the power abstraction is power measurement. “Power measurement accuracy is better at lower levels of abstraction. Hence, the challenge is to elevate the accuracy of power measurement to the system level. One idea that is helpful here is to make the RTL power analysis physically aware. Because most power in any design is consumed by registers, clocks and memories, there should be ways to estimate the power of these components with high accuracy at the RTL level. Sequential switching activity propagation enables accurate propagation of switching activities across the logic boundaries. Modeling clock tree synthesis and the switching power due to interconnects can improve the accuracy further. Finally, any implementation details, such as use of multi-threshold libraries, will enable better accuracy in power computation.”
Interestingly, when it comes to addressing the low-power requirements of today’s mobile devices, Moshe Sheier, director of product marketing at CEVA said whether it is a smartphone or wearable, more and more vendors are turning to a hierarchical processing approach. “With a hierarchical processing approach, dedicated processors are turned on one after the other — from smallest to largest, as required for increasing in complexity tasks. For example, a tiny always-on DSP will always be active, serving natural user interface functions such as voice trigger/command, face/gesture detection and contextual awareness. A larger multimedia DSP will turn on to handle high-quality audio playback, or image-object recognition being offloaded from the main CPU using today’s Android KitKat offloading and tunneling mechanisms. At the last stage, the power-hungry CPU/GPU cluster kicks in to handle general-purpose applications.”
Thermal matters and software
Another emerging trend is in the area of thermal management, which is inter-linked with power models, Kulkarni asserted. Thermal issues are exacerbated due to higher dynamic power consumption with higher operating frequencies and harsher environments, such as in automotive applications. “Power and thermal policies must be part of the overall system design methodology, such as electro-thermal simulation at a higher abstraction level such as a System C/TLM models.”
And last but not least, Schirrmeister pointed to the significant impact of software. “There are activities going on to raise the level of representation of hardware blocks and chip topologies to the ‘scenario’-level, such as making more hardware information available to allow software to more efficiently control which hardware regions can be switched on and off.”