Getting A Handle On RTL X-Verification Challenges

Optimistic simulation behavior can hide bugs in your design that don’t show up until after tapeout.

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The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed.

In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering up logic, any X’s must be cleared on reset or within a specific short number of cycles afterword.   The situation is now much more uncertain for designers whether all possible power scenarios are considered and all X’s will be cleared correctly.

But can’t I throw a switch on my simulator to make all of my  decision logic X-safe and eliminate the optimistic behavior?  You can, but there are drawbacks.  First the throughput of your simulations will drop dramatically and  runtimes will grow a minimum of 3X.  Second, some logic in designs is sensitive to X-optimism and other logic is not.   A brute force approach leaves designers to decide on their own whether they see a real problem or not.  Finally there is no industry standard for X-safe simulation, and the approach taken by one vendor’s tool will likely not be available in another’s.

The temptation is to supply a reset to all the flops in your design, but this will be costly in terms of precious routing density and power usage. Ideally, you would have a static tool that could analyze the rest scheme of your design and then suggest a minimum sub-set of flops that need reset lines.  This week, on March 25, Real Intent unveiled major enhancements in its  Ascent XV product for early detection and management of unknowns (X’s) in digital designs, which address this issue.

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Ascent XV resettability analysis and optimization determines which flops will be reset with a number of cycles and which ones that will be not, and suggest the minimum set that is needed.  There is a similar analysis for retention cells.

Ascent XV also does a static analysis of the design to determine which logic is X-sensitive and allows you to ignore X’s that will not cause problems and to focus on those that need attention.  This is very important when you have to deal with large designs and maybe overwhelmed by simulation results.  Results of this analysis can see in the Verdi debug environment from Synopsys.

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Screen shot of a Synopsys Verdi debug environment showing the propagation from an X-source (red X on the far left) to X-sensitive logic on the bottom right marked with a yellow X.

To hear more on the features and benefits of the new Ascent XV release including reset and retention optimization, watch this video interview with Lisa Piper, Sr. Technical Marketing Manager at Real Intent.