FPGA VHDL Verification

By Espen Tallaksen This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost. All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good to... » read more