Avoiding The Barriers For Multi-Board Systems Design Development


Designing electronic systems that comprise multiple interacting boards, connectors and cables requires a multi-discipline team collaboration to effectively manage design complexity for optimum product performance and reliability. Multi-board systems may comprise two boards or up to hundreds of boards, packing a cabinet or rack, with interconnected connectors and/or cables. Since the hardware fu... » read more

Who’s Profiting From Complexity


Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

HW Vs. SW: Who’s Leading Whom?


In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Are Models Holding Back New Methodologies?


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirrmeister, group director... » read more

Automated Assertion-Based Verification Methodologies For IP And SoC Development


The rapid growth in complexity and size of modern System on Chip devices (SoCs), along with the expense of developing these ICs, has driven the need for design reusability. Today, SoC designs are typically built as a collection of individual IP (Intellectual Property) blocks stitched together with glue logic. These IP can be sourced from multiple design teams, including many 3rd-party teams. So... » read more

Are Models Holding Back New Methodologies


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirmeister, group director,... » read more

Experts At The Table: The Trouble With Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more