Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?

Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.

Advanced packaging shifts to mainstream with complete flows, better tools, market proof points.

LiDAR firms attract investments as corporate and venture investors vie for a piece of this burgeoning market.

The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table.

Design challenges and tool flow gaps emerge, but so do real-world PPA metrics.

As cloud services adoption soars, datacenter chip requirements are evolving.

Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts?

Modern electronics relies heavily on antennas, but companies still make mistakes. That’s about to change.

Dynamic power density and rising leakage power becoming more problematic at each new node.

At 10nm and 7nm, overdesign can affect power, performance and time to market.

Building a power delivery network with the low implementation overhead becomes more problematic at advanced nodes.

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit?