What the move to the next couple process nodes really mean to the semiconductor industry are unknown.
For the better part of the past decade the most advanced companies and the big foundries were targeting 22nm as the bogeyman of chip development. Now it appears the big problems will crop up at 15nm.
That means two things. First, the problems that were expected to crop up at 22nm—leakage, electromigration, electrostatic discharge, layout and even verification—appear to have been pushed off by one node the way strain engineering and immersion and double patterning have managed to rescue bulk CMOS and lithography, respectively, for several nodes.
Second, it means that the problems that have been averted at 22/20nm will be piled up with other problems that have been averted. For the most advanced chip developers working at the bleeding edge of Moore’s Law, this is not good news.
The unanswered question is just how much of the industry will be reeling from this bad news. Memory makers and Intel will certainly feel the pinch, and so will some of the high-volume smart-phone chipmakers, but if 3D stacking lives up to its promise the bigger issues may be well outside the physical layout and process world. They may be in areas such as IP integration, software development and integration, packaging, self test and correction, and verification.
The schism that is developing may no longer just be between the big and the small and the haves and the have nots. It may be between those with big physical problems, and those with virtual problems, and size may no longer be the key differentiator between a company that’s highly profitable and one that’s not, or between those able to wield the most leverage and those that can’t.
–Ed Sperling
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