August 2011 - Page 2 of 3 - Semiconductor Engineering

Which Came First?
By Jon McDonald - 25 Aug, 2011 - Comments: 0

By Jon McDonald Which came first the chicken or the egg? Based on some of my recent discussions I could ask the question in a slightly different way: “Which came first, the hardware or the software?” Depending on your point of view and personal bias the answer may appear obvious, but from what I've seen it can be very dependent on your current engineering situation. Adopting one perspectiv... » read more

Are Test Engineers More Highly Evolved?
By Kiran Vittal - 25 Aug, 2011 - Comments: 0

In a December 2010 blog, my colleague Ron Craig wrote that 94% of respondents to a survey said that timing constraints were a problem. Well, no surprise there. But 70+% said they planned to simply “try harder” during their next project to avoid these problems. Did they really think that was a viable solution? That blog featured a good illustration of the problem. It gave me a good laugh.... » read more

Tech Talk: Graphic Headaches
By Ed Sperling - 24 Aug, 2011 - Comments: 0

Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes. [youtube vid=3Nc77aVH94g] » read more

Experts At The Table: Multi-Foundry Strategies
By Ed Sperling - 22 Aug, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president ... » read more

Does SOI matter to the designers using the chips?
By Various Writers - 19 Aug, 2011 - Comments: 0

By Adele Hars Much of the SOI vs. bulk discussion zeros right in on the manufacturing bottom line:  which is cheaper?   And absolutely, customers want the most cost-effective solution.  But the best of all possible worlds is if you can save them money and give them all the bells and whistles they're looking for, too, right? [caption id="attachment_150" align="alignleft" width="150" capti... » read more

Business First
By Ed Sperling - 19 Aug, 2011 - Comments: 0

The move to stacked die poses some interesting technology challenges and promises significant technology benefits, but the real driver is business—and for this market to work, it has to continue being about business. In the past it was technology first, business last. We are now at the stage where it is business first, technology last. Re-use of entire die as subystems, better use of desig... » read more

New Stacking Issues
By Norman Chang - 11 Aug, 2011 - Comments: 0

Reduced form factors, higher performance, and the demand for lower power necessitate the need for 3D-IC/silicon interposer designs with through-silicon vias (TSVs). That also creates major design challenges in three areas. The verification of power, signal, and reliability integrity—particularly with multi-stacked die on silicon interposer with TSVs—presents issues that can only be overcome... » read more

Customer Perspective: STMicroelectronics
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market. LPE: What do you see as the biggest changes ahead? Magarshack: One is the sheer size of the ecosy... » read more

Getting The Balance Right
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

Defining the power architecture for a low-power design means striking a balance between the high-level abstraction and measurements made typically at RTL and below, but today that is easier said than done. “The balance is that at the high level of abstraction, the design choices you make have a big effect over power, yet your ability to measure them is incomplete until you get much further... » read more

Dueling Power Formats
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Multiple power formats and increasingly complex SoCs don’t sound like a winning formula. So just how bad have things become? Low-Power Engineering asked Sorin Dobre, senior staff engineer at Qualcomm, for a real-world assessment of the situation. LPE: There are three power formats—CPF, UPF and IEEE 1801. How big a problem is this for Qualcomm? Dobre: Actually we have CPF... » read more

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