January 2013 - Page 2 of 5 - Semiconductor Engineering

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 31 Jan, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

Managing Functional Verification Projects
By Various Writers - 31 Jan, 2013 - Comments: 0

The adoption of advanced verification languages and methodologies requires evolution of project management techniques in addition to the change in engineering practices. Managers must be able to assess and manage key project elements such as team expertise, verification methodology, verification IP (VIP) selection and environment setup to successfully deploy high-level verification environments... » read more

Mixed-Signal Technology Summit Proceedings
By Various Writers - 31 Jan, 2013 - Comments: 0

On September 20 Cadence held the second Mixed-Signal Technology Summit. Experts from Cadence and other leading companies presented the latest mixed-signal design methodologies. If you missed the event, you can still view the material via the below archived proceedings. To view the presentations and videos, click here. » read more

It’s The Data, Stupid!
By Frank Schirrmeister - 30 Jan, 2013 - Comments: 0

By Frank Schirrmeister January is prediction month! After writing my 10 year Look-Back on Technology last week, I attended an IDC briefing called “Riding the Momentum: IDC Software Predictions 2013.” IDC is looking at the IT world from four angles that they call four pillars: Cloud, Big Data/Analytics, Social Business and Mobility. In the opening presentation—called “In a Diverse Wo... » read more

ESL Challenges
By Ed Sperling - 26 Jan, 2013 - Comments: 0

System-Level Design talks about the challenges of ESL with Cadence's Ran Avinun, Synopsys' Johannes Stahl, Mentor Graphics' Thomas Bollaert and Forte Design Systems' Brett Cline.   [youtube vid=HftMM71Epqo] » read more

Experts At The Table: Latency
By Ed Sperling - 25 Jan, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance engineering sat down to discuss latency with Chris Rowen, CTO at Tensilica; Andrew Caples, senior product manager for Nucleus in Mentor Graphics’ Embedded Software Division; Drew Wingard, CTO at Sonics; Larry Hudepohl, vice president of hardware engineering at MIPS; and Barry Pangrle, senior power methodology engineer at Nvidia. What follows are exce... » read more

Supersizing Wafers
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Katherine Derbyshire Get ready for 450mm wafers. First seriously considered in 2005, these supersized wafers, along with the equipment to handle, measure, and process them, have gradually made their way to the top of the semiconductor industry’s priority list. But what exactly does that mean? What will 450mm fabs look like, and how will they differ from the 300-mm fabs being built toda... » read more

What Will Replace Dual Damascene?
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations. Dual damascene remains the workhorse... » read more

Inside The Package
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house. SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for year... » read more

Reducing The Drama In DFM
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

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