February 2014 - Page 4 of 9 - Semiconductor Engineering

Many Stresses Impact TSVs
By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

Executive Insight: Luc Van den hove
By Mark LaPedus - 20 Feb, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss current and future process technology challenges with Luc Van den hove, president and chief executive of Imec. What follows are excerpts of that conversation. SE: The industry is simultaneously working on several new and expensive technologies. This includes extreme ultraviolet (EUV) lithography and the next-generation 450mm wafer size. The indu... » read more

Driving Innovation: From Talk to Action
By Karen Savala - 20 Feb, 2014 - Comments: 0

During the recent SEMI Industry Strategy Symposium, one of the themes focused on the challenges of building an innovative workforce with fresh ideas. KLA CEO and president Rick Wallace’s opening keynote address included an appeal for industry to actively recruit more young talent to foster greater levels of innovative thinking. He said that only four percent of the U.S. workforce is compos... » read more

Interconnect Challenges Grow
By Mark LaPedus - 20 Feb, 2014 - Comments: 0

Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

Why Would IBM Sell Its Semi Group?
By Ed Sperling - 20 Feb, 2014 - Comments: 1

Rumors are always just rumors until proven otherwise in business, but in the case of IBM’s semiconductor business, hints about the sale of its semiconductor business are particularly noteworthy. Much has changed since the days when IBM—as International Business Machines—went head-to-head with AT&T’s quasi-public Bell Labs and Xerox’s Palo Alto Research Center (PARC). The breakup of... » read more

New Rules For DRAM
By Jim Feldhan - 20 Feb, 2014 - Comments: 0

By Jim Feldhan DRAM revenues grew by more than 30% in 2013. Average selling prices increased more than 45% as capacity constraints especially for LPDRAM, motivated the transition from 2GB density parts up to 4GB DRAM units declined by almost 10%. Revenue growth rates of more than 30% combined with a declining unit base are not new to the memory market. But 2013 was a pivotal year for DRAM. ... » read more

Does It Take A Catastrophe?
By Linda Prowse Fosler - 20 Feb, 2014 - Comments: 0

What makes a company search for new verification methods and tools? Sometimes organizations change, proactively, because they are wise and want to avoid problems; but sadly, more often it is a catastrophe that forces change. This was the case with a large U.S. supplier of safety-critical and high-reliability ICs. After a failed chip, it finally moved from simply verifying the analog and digi... » read more

Lithography-Enabled Scaling Challenges
By Ehud Tzuri - 20 Feb, 2014 - Comments: 0

The semiconductor industry is being challenged as never before when it comes to lithography-enabled scaling. While development of new patterning techniques and resists as well as inspection and metrology capabilities have helped device scaling advance, major issues continue to challenge the future of Moore’s Law. There’s an industry shift from lithography-enabled 2D devices to materials-ena... » read more

Looking Beyond Moore’s Law
By Mark LaPedus - 20 Feb, 2014 - Comments: 2

For decades, chip scaling has followed a simple linear curve. In this curve, the transistor gate-pitch scales at 0.7x every two years. This is the driving force behind Moore’s Law, which states that the number of transistors per chip roughly doubles every two years. But starting at the 16nm/14nm node, there is a change taking place in chip scaling. According to a chart from Imec, there are... » read more

Impact Of Illumination On Model-Based SRAF Placement For Contact Patterning
By Various Writers - 19 Feb, 2014 - Comments: 1

Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and for random log... » read more

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