September 2014 - Page 3 of 11 - Semiconductor Engineering

Time To Market Concerns Worsen
By Ed Sperling - 25 Sep, 2014 - Comments: 1

Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern. Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over th... » read more

Is IC Design Methodology At The Breaking Point?
By Randy Smith - 25 Sep, 2014 - Comments: 0

Evidence is mounting that traditional “waterfall” methods used to develop complex ICs are reaching the breaking point. Consider that today: Some IC designs contain more than 100 [getkc id="43" comment="IP"] blocks that must be integrated from multiple sources Design requirements are constantly in flux Demands for low power and security are increasing as device connectivity grows S... » read more

Leveraging Virtual Prototypes For Hybrid Emulation
By Tom De Schutter - 25 Sep, 2014 - Comments: 0

As highlighted in many of my blog posts, virtual prototyping has really established itself as the key methodology to shift left software development by decoupling the dependency of software development from hardware availability. The success of the “Better Software. Faster!” book illustrates the wide spread interest in the methodology. The success of virtual prototypes also has led users... » read more

Quantifying IP Entitlement For 14/16nm Technologies
By eSilicon - 24 Sep, 2014 - Comments: 0

The scaling benefits of [getkc id="74" comment="Moore"s Law"] are being seriously tested at 28nm. It is no longer a given that the cost per gate will go down at leading edge process nodes below 28nm, e.g., 20nm though 14nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex [getkc id="81" comment="SoC"] (So... » read more

Verification Planning And Requirement Tracking For Analog Design
By Mentor, a Siemens Business - 24 Sep, 2014 - Comments: 0

Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend comm... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores
By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

Blog Review: Sept. 24
By Ed Sperling - 24 Sep, 2014 - Comments: 0

Cadence’s Brian Fuller captures Chris Rowen’s phylum classifications for data-efficient design—lots of insects and much bigger but fewer mammals. There are cognitive layers in between, as well. Check out the chart. Mentor’s Robin Bornoff digs into thermal runaway and how to determine when it will occur—and burn up a chip. There’s a video to illustrate just what can go wrong. ... » read more

Manufacturing Bits: Sept. 23
By Mark LaPedus - 23 Sep, 2014 - Comments: 0

The annual IEEE International Electron Devices Meeting (IEDM) will take place in San Francisco from Dec. 15-17. As usual, there will be presentations on the latest technologies in a number of fields, such as semiconductors, bio‐sensors, energy harvesting, power devices, sensors, magnetics, spintronics, two-dimensional electronics, among others. Here’s just some of the papers that will be pr... » read more

Power/Performance Bits: Sept. 23
By Ann Mutschler - 23 Sep, 2014 - Comments: 0

Improved liquid battery Researchers at MIT, led by a materials chemistry professor, have improved a proposed liquid battery system that could enable renewable energy sources to compete with conventional power plants. Professor Donald Sadoway and some colleagues have already started a company to produce electrical-grid-scale liquid batteries, with layers of molten material that automatically... » read more

System Bits: Sept. 23
By Ann Mutschler - 23 Sep, 2014 - Comments: 0

Contender emerges for 3D IC semiconductor material While silicon has few serious competitors as the material of choice in the electronics industry, transistors cannot keep shrinking to meet the needs of next-gen devices given the significant physical limitations of energy consumption and heat dissipation. To address this, researchers at Harvard University have achieved a reversible change in e... » read more

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