3D NAND Market Heats Up

Planar approaches will have trouble scaling after 10nm due to floating gate issues; some companies may shift even sooner.

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By Mark LaPedus
It’s the tale of two promising and separate 3D chip architectures. One technology is slowly taking root, while the other one is heating up.

3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are accelerating their efforts in the arena.

Presently, NAND vendors are on the 2xnm or 1xnm nodes. The prevailing thought was that vendors would scale existing planar NAND at three distinct points down the 1xnm node. Typically, NAND vendors denote those points as 1x, 1y and 1z. Then, after the so-called 1z or 1znm node, planar NAND supposedly would hit the scaling wall, forcing vendors to migrate to 3D NAND.

In fact, 2D NAND will have difficulties scaling beyond 10nm. This is because the critical structure in NAND—the floating gate—is seeing an increase in the dreaded cell-to-cell interference in the word lines.

SanDisk still plans to scale NAND for two more generations until 2016, and then, it will debut 3D NAND. But in what appears to be a switch in strategy, Samsung and SK Hynix plan to develop 2D NAND at the 1x and 1y nodes. Then, “it appears that Samsung is bypassing 1z, similar to SK Hynix,” said Doug Freedman, an analyst with RBC Capital Markets.

Instead of going to 1z, Samsung and Hynix will move directly to 3D NAND. In fact, Samsung will begin sampling parts in the second half of 2013, with production slated for 2014, Freedman said.

“As there is maybe one more shrink left for planar NAND, some manufacturers are making the transition earlier to 3D NAND,” said Greg Wong, an analyst with Forward Insights. “Scaling of planar NAND is nearing its end, and 3D NAND is seen as the way to continue density increases and cost reductions for NAND flash memory.”

With 3D NAND, memory vendors also will move from a costly lithography-centric production environment to a less-expensive etch/deposition flow, said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “The overall cost of the tools will be cheaper with 3D NAND,” Lee said “This is mainly driven by the difference in the number of critical lithography and double-patterning steps.”

3D NAND contenders
Samsung will bring out 3D NAND first, followed in order by SK Hynix, Toshiba and Micron, Forward Insights’ Wong said. In 3D NAND, Samsung hopes to leapfrog the competition and grab the early profits with its so-called terabit cell array transistor (TCAT) architecture.

In TCAT, NAND layers are stacked using an oxide and nitride deposition process. Then, the nitride is removed by an etch process. Finally, the bit and word lines are created using a tungsten fill. TCAT and other 3D NAND architectures are different than 2.5D/3D stack-die technologies, where devices are stacked and connected using TSVs.

Another NAND vendor, SanDisk, has a different strategy. “SanDisk is planning to remain planar until 2016, while competitors begin to develop and produce 3D (NAND) into the market late this year and early next,” said RBC’s Freedman. “SanDisk’s (3D NAND) solutions are being judiciously developed to cater to the high-performance market. The high-performance side of the market will not be ready to qualify 3D for another two to three years.”

Using 193nm immersion lithography, the SanDisk-Toshiba duo is producing 19nm planar NAND with a 19- x 26-nm cell size. Then, at 1y, SanDisk’s goal is to devise planar NAND with a 19- x 19.5nm cell size, with production slated by the end of this year.

Then, unlike Samsung and SK Hynix, SanDisk will scale planar at 1z. “There is no need to rush into 3D” until it is cost effective, said Ritu Shrivastava, vice president of technology at SanDisk. In reality, 2D NAND will remain the mainstream technology for some time. Over time, 3D NAND will move into high-end applications, like solid-state storage.

By 2016, SanDisk hopes to debut the Bit Cost Scalable (BiCS) technology, a 3D NAND technology that was originally conceived by Toshiba. BiCS makes use of a “punch-and plug” structure. Toshiba has fabricated a prototype 32-Gbit BiCS test array, with a 16-layer memory cell based on 60nm design rules.

The advantage of 3D NAND is that it doesn’t require leading-edge lithography. Going to 3D NAND will present some challenges, namely the development of quality parts with good read/write performance with endurance. “3D NAND will require a different equipment set,” Shrivastava said. “The burden will shift from lithography to deposition and etch.”

3D NAND process challenges
It also will present NAND vendors with some difficult decisions. First, despite their public roadmaps, vendors may be forced to migrate to 3D NAND sooner than later. “Most leading-edge producers are doing 2D NAND manufacturing at the 20nm or 19nm node, which is the last generation of self-aligned double patterning technology,” Applied’s Lee said. “By using self-align double patterning, one can pattern about 19nm or 19.5nm half-pitch.”

But for some time, the problem with 2D NAND has been apparent—it is running out of steam. “With existing planar NAND, there is not much room to squeeze in the materials for the charge-trap flash or the floating-gate,” Lee said.

In theory, NAND hits the wall at 10nm. “In order to scale NAND manufacturing beyond that, the industry must adopt self-aligned quadruple patterning or self-aligned triple pattering,” he said. “That allows for 10nm half-pitch. But doing 10nm half-pitch patterning will be extremely difficult. It will add a lot more process steps, which will increase the cost of manufacturing.”

Clearly, 3D NAND is the future based on two factors: scaling and cost. “If you compare the cost between sub-20nm planar versus 3D NAND, I believe it will be a lot cheaper to build a 3D NAND fab,” he said. “Planar is driven by litho. In 3D NAND, the bit growth is enabled by increasing the number of vertical layers. This has nothing to do with litho.”

3D NAND can be produced using existing 193nm lithography. Other expensive steps, such as self-align double-patterning etch and low-temperature atomic layer-deposition (ALD), are also eliminated. All told, 3D NAND is largely dependent on two technologies: deposition and etch.

The big challenge is to enable high-aspect ratios using new etch techniques. “There are three distinctly new etch processes in 3D NAND,” Lee said. “This includes high-aspect ratio memory hole etch, which did not exist in planar NAND. There is also a high-aspect ratio trench-line etch, which also did not exist in planar. And then another one is a so-called staircase etch. This is a very long process, which has to provide the landing pads for the contacts.”

3D NAND also introduces alternating stack deposition, which defines the vertical stack. In a 32-layer NAND device, for example, the process could involve some 64 layers of deposition, plus some dummy layers. All told, the flow requires some 70 alternating deposition steps. “The existing tools cannot provide such high productivity,” Lee said. “So that involves a new type of chamber design and technology.”

Metrology is also a critical part of the equation. “Nanometrics believes that 3D NAND will use 20% to 25% more OCD tools relative to planar NAND,” said Weston Twigg, an analyst with Pacific Crest Securities.

“In planar NAND, the gate width is defined by lithography,” added Applied’s Lee. “Now, the gate width is defined by deposition. So, the uniformity of PECVD deposition of each layer, and the quality of the films, are very critical. When we deposit several layers, it’s not a big deal. But let’s say we deposit 40, 50 or 70 layers in-situ. That means we have to control the surface of the interface very smoothly from the beginning. Otherwise, we end up with a rough surface on the top, which will not work.”

So far, Micron, Samsung, SanDisk-Toshiba and SK Hynix have yet to discuss the exact specifications for their respective 3D NAND devices. It’s unclear how many layers the initial devices will have, prompting many to ask a simple question: How far will 3D NAND scale? “I see it going for several generations,” Lee said. “But after 3D NAND, the industry will require another breakthrough.”