Notes From The Chip Beat

A take on new nodes, FD-SOI and sextuple patterning.


Over the last several months, I’ve attended a number of conferences, such as IEDM, SPIE, the FD-SOI Summit and others. At each conference, there is a dizzying amount of information and data. Eventually, some information turns into an article, while most ends up buried in a reporter’s notebook.

In any case, here are five observations I’ve made, based on those and other events in the past several months:

Sextuple patterning?
At 10nm and 7nm, chipmakers are extending optical lithography and multiple patterning. For 7nm, many will use self-aligned quadruple patterning (SAQP) for the critical features.

But at 7nm/5nm, some hope to insert extreme ultraviolet (EUV) lithography as a means to reduce the patterning steps and costs. At 5nm, EUV is required. But what if EUV is not ready at 7nm and/or 5nm?

Just in case, the industry has been toying with octuple (eight) patterning. Most, however, say self-aligned octuple patterning (SAOP) using optical lithography is too complex. Overlay is a big headache.

At various events, I’ve also heard whispers about sextuple (six) patterning. Over the years, in fact, several papers have been presented on self-aligned sextuple patterning (SASP). It’s unclear if the industry is pouring a lot of resources in this or not. But if they are, SASP would provide an interim step to EUV—or push out EUV even further. Perhaps SASP is wishful thinking. Stay tuned.

More process flavors than customers.
There seems to be a disconnect in the industry. At advanced nodes, chipmakers appear to offer more processes than the actual size of the customer base. At last count, there are about 300 foundry customers at 28nm and above, compared to roughly 10 at 10nm/7nm, according to International Business Strategies.

At the same time, the node offerings are piling up. Some foundry vendors are following the traditional node progression at the leading edge, such as 10nm and 7nm. Then, GlobalFoundries added 12nm FD-SOI to the mix. In addition, TSMC added a 12nm bulk process. And Samsung plans to roll out 8nm and 6nm.

The numbers don’t add up. It’s doubtful that chipmakers will find customers for all processes. The worst case scenario is that some processes will support one or a handful of foundry customers. Not sure that model will pay any dividends in the long term. And, of course, the node names are meaningless as time goes on. The node numbers say one thing, but the specs say another.

Old processes and fabs never die.
Given that there are over 300 foundry customers at 28nm and above, trailing-edge processes and fabs are still here to stay—and for a long time.

Analog is a good example, as the technology is still required for a multitude of systems. Power management ICs, RF and others also don’t require leading-edge fabs.

Here is a key indicator that demand is still strong for 200mm. “During the quarter, the utilization rates in 8-inch fabs as well as 12-inch for the last node approaches near full capacity, driven by the trends in the consumer and communication segments,” said Po Wen Yen, chief executive of UMC, in a recent conference call. “And for our 8-inch, we are fully loaded to meet the growing demand of our customers.”

Will FD-SOI fly?
FD-SOI has been in the works for several years. GlobalFoundries and Samsung are providing foundry services for the technology. NXP, Sony, ST and others are developing chips based on FD-SOI.

Over the years, though, FD-SOI has seen relatively limited adoption for several reasons. For one thing, SOI wafer costs are higher. Customers must devote significant design resources to understand FD-SOI and the nuances of back-bias technology.

So what will it take to get FD-SOI over the hump? At a recent FD-SOI event, Ron Moore, vice president of marketing for the Physical Design Group at ARM, summarized the situation. “Foundry partners have stepped up to provide manufacturing options,” Moore said in a presentation.

But the EDA and IP communities need to step up to provide more tools and methods to help implement FD-SOI designs. “We need the EDA partners to step up and help us learn to do that and give us the implementation methodologies that are as easy to use as the ones we have today that do dynamic voltage and frequency scaling through normal processes and Vt options,” Moore said. “We need to start organizing ourselves to build these IoT reference platforms and do the reference designs. We need to do the silicon proof points that will allow people to say: ‘Yes, I know it’s real. Yes, I know it’s going to work. And yes, I will use that as part of my silicon strategy.’ ”

Memory comeback
At the beginning of the year, the IC forecasts were muted. Many predicted a flat to slightly up year in terms of growth for the IC industry. Some were even predicting a slight downturn.

Now, most analysts are raising their forecast. For example, IC Insights recently raised its worldwide IC market growth forecast for 2017 to 11%—more than twice its original 5% outlook.

Memory is driving the forecast. “The revision was necessary due to a substantial upgrade to the 2017 growth rates forecast for the DRAM and NAND flash memory markets,” according to IC Insights.

“IC Insights currently expects DRAM sales to grow 39% and NAND flash sales to increase 25% this year, with upside potential from those forecasts,” according to the firm. “DRAM market growth is expected to be driven almost entirely by a huge 37% increase in the DRAM average selling price (ASP), as compared to 2016, when the DRAM ASP dropped by 12%. Moreover, NAND flash ASPs are forecast to rebound and jump 22% this year after falling by 1% last year.”

Related Stories
Big Changes In Patterning
The shift to GPU-accelerated mask writing and curvilinear shapes could fundamentally change chip design and manufacturing.
Multi-Patterning Issues At 7nm, 5nm
Variations in different masks, alignment problems and the physical limits of immersion add up to serious issues at 7nm and 5nm.
Uncertainty Grows For 5nm, 3nm
Nanosheets and nanowire FETs under development, but costs are skyrocketing. New packaging options could provide an alternative.
Moore’s Law: A Status Report
The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options.

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