Identify and run only the design rules that are local in scope to reduce runtime and hardware requirements.
By John Ferguson and Lei Ling
The increasing complexity of integrated circuit (IC) designs is straining our traditional design rule checking (DRC) methods. The iterative “construct by correction” approach that worked well for simpler, custom layouts is now creating substantial runtime and resource bottlenecks, hindering design teams’ ability to efficiently verify their advanced designs and meet aggressive time-to-market targets. A proven solution is found in verification strategies supported by design automation tools that offer powerful shift-left capabilities.
The core challenge lies in the changing nature of modern IC design. What was once a manual, custom process has given way to highly automated workflows and multi-layered design hierarchies. With different design components being developed by disparate teams on different timelines, it has become extremely difficult to have a fully assembled design layout available for comprehensive verification. Additionally, the sheer volume and complexity of today’s advanced process design rules have exacerbated the runtime and compute requirements for DRC.
The solution lies in shifting verification steps earlier in the design process—a strategy known as “shift-left” verification. By moving verification closer to the source of design changes, shift-left approaches can significantly reduce debug time, manage incomplete data, and expedite the path to tape-out. The runtime and memory difference between a traditional DRC run and a shift-left DRC run is significant, as shown in figure 1.
Fig. 1: Runtime and memory improvements of Calibre nmDRC Recon compared to Calibre nmDRC.
Major semiconductor companies are having success with the shift-left DRC tool from Siemens EDA, called Calibre DRC Recon. The key to this tool’s effectiveness lies in its ability to identify and run only the rules that are local in scope, rather than executing a comprehensive DRC check across the entire design. This “local checks” approach drastically reduces runtime and hardware requirements compared to traditional DRC methods.
Complementing the local checks approach, designers can also use an auto-waivers feature to identify and exclude regions of the design that are known to be incomplete, eliminating them from checking so false violations don’t slow down the verification process. This is a grey-boxing technique achieved with auto-waivers as illustrated in figure 2.
Fig. 2: The grey-box capability lets designers exclude or include specified regions.
Microsoft, a leading technology company, has seen firsthand the benefits of adopting a shift-left verification strategy using Calibre DRC Recon. The Microsoft design team was able to significantly reduce runtime and hardware requirements while enhancing their overall productivity. The designers started using Calibre nmDRC Recon iterations at the floorplan stage, then at the physical implementation stage. By that point, most of the designs were clean of PG shorts. Figure 3 illustrates runtime improvements for different DRC methods.
Fig. 3: Run times are significantly reduced when using shift-left DRC.
“DRC Recon has been a game-changer for our early design stages,” said Mike Cesky, principal physical design engineer at Microsoft. “It provides a solid foundation that allows our designers to pinpoint violations efficiently, significantly reducing run times and simplifying the debugging process. This tool has truly enhanced our productivity and streamlined our workflow.”
Microsoft’s experience demonstrates the power of shift-left verification in action. By leveraging the local checks approach and complementary features like auto-waivers and split-deck runs, the Microsoft team was able to accelerate their design iterations and reduce time-to-market.
The runtime improvements were substantial, with the shift-left DRC tool delivering up to 15 times faster performance compared to traditional DRC methods. Moreover, the memory usage was reduced by up to 18 times, allowing the design team to maximize the utilization of their compute resources.
As the complexity of IC designs continues to escalate, design teams can no longer rely on traditional DRC methods to keep pace. The shift-left verification strategy offers a compelling solution that addresses the key challenges faced by modern design organizations.
By focusing on local checks, leveraging auto-waivers, and optimizing parallel execution, shift-left DRC accelerates the design and verification process, simplifies debugging, and ultimately brings innovative products to market faster. The Microsoft case study serves as a powerful testament to the transformative impact of this approach, highlighting the significant productivity gains and efficiency improvements that design teams can achieve.
As the semiconductor industry continues to push the boundaries of innovation, embracing a shift-left mindset for physical verification will be crucial for design teams looking to stay ahead of the curve. The advanced DRC tool from Siemens provides a proven path forward, equipping designers with the capabilities they need to navigate the complexities of modern IC design and deliver their cutting-edge products to the market with unprecedented speed and efficiency.
— Lei Ling is a technology consultant at Siemens EDA.
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