A new technical paper titled “A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems” was published by researchers at Hongik University, Seoul, South Korea.
“An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency,” states the paper.
Find the technical paper here. Published November 2022.
J. Jin, S. Kim and J. Kim, “A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems,” in IEEE Access, vol. 10, pp. 124217-124226, 2022, doi: 10.1109/ACCESS.2022.3224451.
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