Another Brick Or Two In The Chip Design Wall

Physical challenges come and go in the semiconductor world. But increasingly, they also stick around, showing up in inconvenient places at the worst time.

The chip industry has confronted and solved some massive challenges over the years. There was the 1 micron lithography wall, which was supposed to be impenetrable. That was followed by the 193nm litho challenge, which cost many billions of dollars and years of work to solve.

There were thermal issues in processors, which forced companies to shift first from single-core architectures to multi-core, and then to dark silicon and ultimately a mix of dark and warm silicon. And then there was the memory wall, versions one and two, where getting enough data in and out of DRAM required an overhaul of the memory architecture.

There also have been a series of materials issues, which is why copper interconnects are being replaced by cobalt at the most advanced geometries. There are other materials in research, as well, to help reduce leakage. And there also are new transistor structures on their way at 5 and 3nm, because finFETs are running out of steam. They are being replaced by nanosheet FETs, which can control gate leakage more effectively. More recently, there are the reliability issues, particularly in automotive applications and in the cloud, which is why everyone is racing to reduce process variation and the variation between chips. The list goes on.

The problem isn’t that these issues cannot be solved. It’s that they’re showing up together, sometimes inconsistently, depending upon the architecture, the process node and the packaging approach. In the past, there used to be a roadmap, aka the International Technology Roadmap for Semiconductors (ITRS), to identify these kinds of issues well in advance. The leading semiconductor companies would argue a lot, test a number of different options, and come to a consensus about what works best from a technology and cost perspective.

The death of the ITRS was based on the assumption that the economic benefits of scaling would end in 2021. It can be argued they already have ended, but there is still demand for larger die and larger packages. In fact, some of the advanced AI chips are so big that they exceed the size of a reticle and have to be stitched together. Cerebras has taken this to an extreme, and created a single chip the size of a wafer—215mm² (There is no mention of yield).

But what the ITRS roadmap did provide was an advance look at issues so they could be managed in a consistent way. The advent of new architectures designed to improve performance by orders of magnitude, myriad packaging options, various new memory types, I/Os, on-chip and off-chip interconnects, silicon photonics, different substrates, and new market demands in verticals that weren’t even part of the ITRS roadmap in the past, are making this much more challenging. Bottlenecks are cropping up everywhere, and they are not necessarily the same bottlenecks from one application to the next, or from one market to the next.

A single device may have multiple processing elements and I/Os developed at multiple process nodes connected to multiple types of memories. There is even work underway on in-memory processing and analog memory storage. So what used to be a series of roadblocks is now looking more like a minefield, and the number of tradeoffs involving for power, performance, cost, reliability and time to market is growing. And what’s changed is that those tradeoffs are no longer just the responsibility of the architects. They now need to be implemented, tested and retested throughout the design cycle, with data fed back even from the field.

At some point, though, the chip industry will have to settle down on some common architectures, approaches, materials, equipment and memories. The big questions are who will drive that and when.