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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

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DAC 2015: Day 4
By Brian Bailey - 11 Jun, 2015 - Comments: 0

Are you ready for the self-driving car? Threats come from other cars – not necessarily hitting you but hacking you. Day four of DAC started with a keynote panel moderated by John McElroy of Blue Sky Productions and panelists included Jeff Massimilla from General Motors and Craig Smith from Theia Labs/OpenGarages.org/IATC. "What would happen if cars started picking up viruses," asked Anne C... » read more

DAC 2015: Day 3
By Brian Bailey - 10 Jun, 2015 - Comments: 0

The schedule for today revolves around eating and it is perfectly balanced between the big three. The morning starts with breakfast for the Cadence panel titled "Crossing the Great Divide: How to Safely Navigate the move from 28nm to 16FF+." The panel was moderated by Brian Fuller and panelists included Jayanta Lahiri from ARM, Afshin Montaz from Broadcom, Scott McCormack from Freescale, Yan... » read more

DAC 2015 Day 2: Keynotes, Tutorials and More
By Brian Bailey - 09 Jun, 2015 - Comments: 0

Walking to DAC, you had to pass the Apple Developers Conference. The line to get in wrapped all the way around the block and there were many peaceful protests directed towards them. Large TV trucks, trucks from CNN, MSNBC and many others lined the streets to hear about new capabilities coming to the group of people who create the Apps for Apple devices. None of them were probably even aware tha... » read more

Full Coverage Or Full Monty?
By Brian Bailey - 09 Jun, 2015 - Comments: 0

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

DAC 2015: Day One
By Brian Bailey - 08 Jun, 2015 - Comments: 0

It requires a certain dedication to attend technical DAC sessions on a Sunday morning, but full day workshops start before 9:00am for those dedicated to hearing about the latest work being conducted in academia and the research arm of industry. These are highly technical sessions that target academics and those serious about keeping a pulse on up and coming technologies. One such workshop wa... » read more

Memory Design At 16/14nm
By Brian Bailey - 28 May, 2015 - Comments: 0

As we get older the memory may start to fade, but that is not a viable option if we are talking about embedded memory. Chips contain increasing amounts of memory, and for many designs memory consumes more than half of the total chip area. “At 28nm we saw a few people with greater than 400Mbits of memory on chip,” says Prasad Saggurti, product marketing manager for Embedded Memory IP at [... » read more

Full Coverage Or Full Monty
By Brian Bailey - 28 May, 2015 - Comments: 1

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Rethinking Patents
By Brian Bailey - 28 May, 2015 - Comments: 0

Over the past few years the pressure on the patent system as a means of protecting intellectual property has been tested to the limit, and many changes are being made in an attempt to keep it viable. But in an age of globalization, coupled with the fact that for the patent system to work there has to be an infrastructure of suitable enforcement, it may be time to rethink its viability—especia... » read more

Problems Ahead for EDA
By Brian Bailey - 19 May, 2015 - Comments: 0

Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Trouble Ahead For IP industry?
By Brian Bailey - 14 May, 2015 - Comments: 0

[getkc id="106" kc_name="Power-aware design"] has risen from an afterthought to a primary design constraint for some design types. Initially it was smart phones and other battery operated devices. It has consistently expanded into additional areas including those plugged into the wall and those plugged into the grid. Some parts of the world are imposing restrictions on the power that a device c... » read more

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