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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Less Moore Means More Intelligence
By Brian Bailey - 23 Apr, 2015 - Comments: 3

It would seem as if the entire industry is flooding the forums with articles about [getkc id="74" comment="Moore's Law"], as it reaches its 50th birthday (April 19th) and that this represents the longest and most important exponential in the history of man. The numbers and that impact are everywhere and I do not intend to repeat them. There are lots of articles talking about when Moore’s law ... » read more

Tech Talk: Virtual Prototyping
By Brian Bailey - 22 Apr, 2015 - Comments: 0

Bill Neifert, CTO of Carbon Design Systems, talks with about the intersection of IP and EDA, driven in particular by ARM's new architecture. [youtube vid=1OopYWmRarE] » read more

The Wild West Of Automotive
By Brian Bailey - 09 Apr, 2015 - Comments: 0

Automotive is considered one of the great new markets for EDA and IP. Electronic complexity is increasing rapidly, product update cycles are decreasing, and new standards mean that many of the old ways of doing development are no longer possible. Such change creates opportunity, along with a certain degreed of confusion. As the number of discrete systems increases, so do costs. Electronics c... » read more

Does Fast Simulation Help Debug Productivity?
By Brian Bailey - 09 Apr, 2015 - Comments: 0

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

First Time Success and Cost Control
By Brian Bailey - 01 Apr, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Is SystemC Broken?
By Brian Bailey - 26 Mar, 2015 - Comments: 19

In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry needs a viable [getkc id="104" kc_name="virtual prototype"]. That requires a suitable language in order to express necessary concepts at a high enough level of [getkc id="101" kc_name="abstraction"] s... » read more

Design By Architect Or Committee?
By Brian Bailey - 26 Mar, 2015 - Comments: 5

Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

Patents And EDA Making Waves
By Brian Bailey - 26 Mar, 2015 - Comments: 0

If the old adage “may you live in interesting times” is true, then lawyers must be wondering if they should be very happy or scared. The rate at which [getkc id="16" comment="patent"] law, and patents in general, are changing should give everyone pause – including the future competitiveness of the United States and the value of patents to EDA. The World Intellectual Property Organizati... » read more

First Time Success And Cost Control
By Brian Bailey - 13 Mar, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

The Interconnected Web Of Power
By Brian Bailey - 12 Mar, 2015 - Comments: 0

Tradeoffs between area and timing used to follow fairly simple rules. You could improve timing by adding area, and occasionally find an architectural solution that would decrease both at the same time. With physical synthesis the relationship became a little more complicated because an increase in area, say to make a drive larger or add another buffer, might upset the layout. That, in turn, cou... » read more

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