Author's Latest Posts

A Method To Quickly Assess The Analog Front-End Performance In Communication SoCs
By Synopsys - 05 Nov, 2014 - Comments: 0

This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and oper... » read more

Extending Digital Verification Techniques For Mixed-Signal SoCs With VCS AMS
By Synopsys - 22 Oct, 2014 - Comments: 0

The growth in mixed-signal system-on-chip (SoC) designs is driven by many factors, including cost, performance and power consumption. This is fueled by many industry segments, including mobile communication, automotive, imaging, medical, networking and power management. The convergence of analog and digital blocks within the same die is driving the need for SoC design teams to adopt new verific... » read more

Meeting The USB IP Requirements Of SoC Designs From 180-nm To 14/16nm FinFET
By Synopsys - 08 Oct, 2014 - Comments: 0

The ubiquitous USB standard provides data and charging capabilities to a multitude of consumer and enterprise products. USB’s ease-of-use and wide availability is belied by USB IP designers’ technical innovations. Without these innovations, USB could not be enabled in a broad range of process technologies ranging from 180-nm to the latest 14/16-nm FinFET technologies. This white paper ad... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores
By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

How VXLAN-Based Ethernet IP Solves Cloud Computing Network Bottlenecks
By Synopsys - 10 Sep, 2014 - Comments: 0

Network virtualization technologies running over optimized Ethernet IP are enabling cloud computing data centers to expand and support the growing amount of internet traffic. Hyperscale cloud data centers are driving requirements for new network overlay protocols such as Virtual Extensible LAN (VXLAN) running over Ethernet. This whitepaper discusses in detail the benefits of VXLAN and how it ca... » read more

Transaction Debug
By Synopsys - 21 Aug, 2014 - Comments: 0

SoC design is complex. It involves both software and hardware design that calls for a higher level of abstraction to ensure accurate verification. Transaction-level verification and debug offers this higher abstraction, while staying close to actual hardware signals. Traditionally, its use has been limited by the lack of a better mechanism and database to capture the critical information needed... » read more

Leveraging Processor Extensibility To Build An Ultra Low-Power Embedded Subsystem
By Synopsys - 06 Aug, 2014 - Comments: 0

There is increasing demand for electronic devices to execute more functions while consuming less power and silicon area. To achieve this, systems instantiating multiple, heterogeneous processor cores optimized for low power and high performance are gaining popularity among design teams. In these systems, one or more deeply embedded processors execute a limited set of dedicated applications. The... » read more

More Effective Test: Slack-Based Transition Delay
By Synopsys - 23 Jul, 2014 - Comments: 0

Semiconductor companies have come to rely on delay testing to attain high defect coverage of manufactured digital integrated circuits (ICs). Delay testing uses transition delay (TD) patterns created by automatic test pattern generation (ATPG) tools to target subtle manufacturing defects in fabricated designs. Although standard TD testing improves defect coverage beyond levels stuck-at patterns ... » read more

Ultra Low-Power 9D Sensor Fusion Implementation
By Synopsys - 09 Jul, 2014 - Comments: 0

This paper presents a case study on computing the 3D orientation of a device by means of a 9D fusion algorithm. The focus is on optimizing the fusion algorithm for execution on the DesignWare Sensor IP Subsystem. Performance measurements show the benefits of using ARC Processor EXtension (APEX) accelerators, which improve both cycle count and energy consumption in comparison to other commercial... » read more

Using VDKs For Automotive Systems Development
By Synopsys - 25 Jun, 2014 - Comments: 0

The software content of automotive systems found in powertrain, chassis, safety, body and advanced driver assistance systems (ADAS) application is increasing. At the same time, the pressure to accelerate development time lines, improve reliability and maintain/reduce costs is also increasing. Automotive OEM, Tier 1 and semiconductor companies involved in embedded software development, integrati... » read more

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