Author's Latest Posts


On-Package Memory With UCIe To Improve Bandwidth Density And Power Efficiency (AMD, Intel Corp.)


A new technical paper titled "On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach" was published by researchers at Intel Corporation and AMD. Abstract "Emerging computing applications such as Artificial Intelligence (AI) are facing a memory wall with existing on-package memory solutions that are unable to meet ... » read more

LLM-Based AI Agent That Automates The Transistor Sizing Process (Univ. of Edinburgh)


A new technical paper titled "EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit" was published by researchers at The University of Edinburgh. Abstract "The design of Analog and Mixed-Signal (AMS) integrated circuits (ICs) often involves significant manual effort, especially during the transistor sizing process. While Machine Learning techniques in Electronic Design A... » read more

Framework for Optimizing Reliability and Thermal Management of 3DICs (National Taiwan Univ., Lamar Univ.)


A new technical paper titled "The Impact of Process Variations on the Thermo-Mechanical Behavior of 3D Integrated Circuits" was published by researchers at National Taiwan University and Lamar University. Abstract "The use of vertically stacked architectures in three-dimensional integrated circuits (3DICs) offers a transformative path for advancing Moore’s Law by significantly boosting co... » read more

AI-Empowered Analog IC Sizing Methods (Univ. of Glasgow Et Al.)


A new technical paper titled "From Systematic to Intelligent: Assessing AI-Empowered Optimization Techniques for Analog Building Block Sizing" was published by researchers at University of Glasgow, Mediatek, The University of Edinburgh, Magics Technologies NV, University of Sevilla and Georgia Institute of Technology. Abstract "This paper presents a comprehensive, design-insight-based compa... » read more

Purity Requirements in the Semiconductor Industry (RMIT, ICTEAM, U. of Edinburgh)


A new technical paper titled "Purer than pure: how purity reshapes the upstream materiality of the semiconductor industry" was published by researchers at Royal Melbourne Institute of Technology, Université catholique de Louvain, and University of Edinburgh. Abstract "Growing attention is given to the environmental impacts of the digital sector, exacerbated by the increase of digital produ... » read more

Monolithic Integration of Air-Clad Optical Through-Silicon Waveguides in Silicon (TH Wildau et al.)


A new technical paper titled "Monolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects" was published by researchers at the Technical University of Applied Sciences Wildau, TU of Applied Sciences Mittelhessen, TU Ilmenau, Brandenburg University of Technology and Fraunhofer IPMS. Abstract "The scaling limitations of electrical interconnects are ... » read more

Wafer Warpage Evolution During Key Backside Power Delivery Network Fabrication Steps (Korea Univ., Georgia Tech)


A new technical paper titled "Process-Induced Warpage Behavior in Backside Power Delivery Network Fabrication" was published by researchers at Korea University and Georgia Institute of Technology. Abstract "As semiconductor devices continue to scale, backside power delivery networks (BSPDNs) have emerged as a promising alternative to conventional front-side power delivery networks (FSPDNs),... » read more

First Stage Of Nanoscale Imaging In Positive-Tone EUV Photoresists: The Impact Of Polymer Sequence (Berkeley Lab, Columbia Hill)


A new technical paper titled "Initial stage of nanoscale imaging in positive-tone extreme UV photoresists: the influence of polymer sequence" was published by researchers at Lawrence Berkeley National Laboratory and Columbia Hill Technical Consulting. Abstract "Photolithographic patterning using extreme ultraviolet (EUV, 92.5 eV) light is a radiolytic process that initially forms electrons,... » read more

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)


A new technical paper titled "CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing" was published by researchers at University of California, Riverside. Abstract "Secure communication is a critical requirement for Internet of Things (IoT) devices, which are often based on Microcontroller Units (MCUs). Current cryptographic solutions, which rely on software librari... » read more

Algorithms For Black-Box, Physical-to-DRAM Address-Mapping Recovery (Georgia Tech, CNRS, Et Al.)


A new technical paper titled "Knock-Knock: Black-Box, Platform-Agnostic DRAM Address-Mapping Reverse Engineering" was published by researchers at Georgia Tech, ESILV, CentraleSupelec, Inria, CNRS, IRISA. Abstract "Modern Systems-on-Chip (SoCs) employ undocumented linear address-scrambling functions to obfuscate DRAM addressing, which complicates DRAM-aware performance optimizations and hind... » read more

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