Author's Latest Posts

Study Of Multi-Die And Multi-Technology Floorplanning (Texas A&M, Duke)
By Technical Paper Link - 05 Apr, 2025 - Comments: 0

A new technical paper titled "PPAC Driven Multi-die and Multi-technology Floorplanning" was published by Texas A&M University and Duke University. Abstract "In heterogeneous integration, where different dies may utilize distinct technologies, floorplanning across multiple dies inherently requires simultaneous technology selection. This work presents the first systematic study of multi-die ... » read more

Emerging Cybersecurity Risks in Connected Vehicles, With Focus On In-Vehicle and Vehicle-Edge Platforms
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "Security Risks and Designs in the Connected Vehicle Ecosystem: In-Vehicle and Edge Platforms" was published by researchers at Università di Pisa, Ford Motor Company, MIT, and the Institute of Informatics and Telematics (Pisa). Abstract "The evolution of Connected Vehicles (CVs) has introduced significant advancements in both in-vehicle and vehicle-edge platfor... » read more

Thermal Slip Length at a L/S Interface: Power Law Relations From Spatial and Frequency Attributes of the Contact Layer (Caltech)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "Thermal Slip Length at a Liquid/Solid Interface: Power Law Relations From Spatial and Frequency Attributes of the Contact Layer" was published by researchers at California Institute of Technology, , T. J. Watson Sr. Laboratories of Applied Physics. Abstract "Specialty integrated chips for power intensive tasks like artificial intelligence generate so much heat ... » read more

Photonic-SRAM Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems (UW, USC, GF)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems" was published by researchers at University of Wisconsin–Madison, USC and GlobalFoundries. Abstract "In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabri... » read more

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions" was published by researchers at Politecnico di Torino and EPFL. Abstract "Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require... » read more

LLM-based Agentic Framework Automating HW Security Threat Modeling And Test Plan Generation (U. of Florida)
By Technical Paper Link - 01 Apr, 2025 - Comments: 0

A new technical paper titled "ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification" was published by researchers at University of Florida. Abstract "Current hardware security verification processes predominantly rely on manual threat modeling and test plan generation, which are labor-intensive, error-prone, and struggle to scale with increasing ... » read more

Reverse Engineering NVIDIA GPU Cores (Universitat Politècnica de Catalunya)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Analyzing Modern NVIDIA GPU cores" was published by Universitat Politècnica de Catalunya. Abstract "GPUs are the most popular platform for accelerating HPC workloads, such as artificial intelligence and science simulations. However, most microarchitectural research in academia relies on GPU core pipeline designs based on architectures that are more than 15 yea... » read more

Scalable And Energy Efficient Solution for Hardware-Based ANNs (KAUST, NUS)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Synaptic and neural behaviours in a standard silicon transistor" was published by researchers at KAUST and National University of Singapore. Abstract "Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved ... » read more

GPU Analysis Identifying Performance Bottlenecks That Cause Throughput Plateaus In Large-Batch Inference
By Technical Paper Link - 30 Mar, 2025 - Comments: 1

A new technical paper titled "Mind the Memory Gap: Unveiling GPU Bottlenecks in Large-Batch LLM Inference" was published by researchers at Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, and IBM Research. Abstract "Large language models have been widely adopted across different tasks, but their auto-regressive generation nature often leads to inefficient resource util... » read more

Strategies For Reducing The Effective GaN/Diamond TBR
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications" was published by researchers at University of Bristol, Cardiff University and Akash Systems. Abstract "GaN high electron mobility transistors (HEMTs) on SiC substrates are the highest performing commercially available transistors for high-power, hi... » read more

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