Baby Steps Toward 3D DRAM

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive.

Several new ideas are underway for building 3D DRAMs both with and without capacitors.

“Advances in DRAM have been driven by scaling, shrinking the overall footprint as each [process] generation progresses to the next,” said Benjamin Vincent, worldwide senior manager of semiconductor process and integration at Lam Research, in a recent blog.[2] “DRAM is following in the steps of NAND by evolving to three dimensions in order to build more storage per unit area. This is good for the industry because it pushes the technological envelope for memory, and because more bits per square micrometer mean production costs decrease.”

Reducing the cell size is the most obvious way to increase the amount of data storable on a single-layer DRAM chip. But the vertical capacitor makes for very thick layers, which are difficult to stack. Some efforts attempt to run the capacitors horizontally. Others eliminate the capacitor altogether. None is ready for prime time, however. And while we’re likely years away from commercial production of such a DRAM, the steps being taken are illuminating.

3D DRAM can mean two things, one of which is already in production. “The most popular use case for 3D DRAM is HBM (high-bandwidth memory),” said Bhavana Chaurasia, senior product manager for HBM interface solutions at Synopsys. “HBM provides the required bandwidth and performance for today’s high-performance data center SoCs.”

But HBM is a stacked-die memory, not a monolithic die in the way 3D NAND flash is. A monolithic 3D DRAM chip could provide an immediate boost if employed in the HBM architecture. “When commercially viable 3D DRAM is available and die stacking challenges such as thermal management have been further addressed, this would be good news for HBM providers as it introduces memory density and energy efficiency improvements that will be impactful for data center and AI applications,” said Daryl Seitzer, principal product manager for embedded memories at Synopsys.

First step is a smaller cell
It’s far easier to optimize a single layer of DRAM cells than it is to stack them up, although “easier” is a relative term. The simplest way is to print smaller features. This can be done either by pushing self-aligned double and quadruple patterning (SADP, SAQP) using 193nm ArF lithography or moving to extreme ultraviolet (EUV) photolithography.

“Most recent steps toward footprint reduction pit EUV patterning against traditional ArF SADP and SAQP processes for cutting-edge 2D DRAM nodes,” said Daniel Soden, business development manager at Brewer Science.

Such advancements will shrink the cell in absolute terms, but it remains the same relative to minimum feature size. Separately, efforts are underway to change the cell architecture so that an area efficiency of 4F² can be achieved (where F is the minimum feature size). Samsung announced such efforts at the IMW 2024 conference. It employs a vertical-channel transistor in a manner that allows placement of capacitors at each word/bit-line intersection and moves from the current 6F² cell to 4F². But it will require new materials, including ferroelectrics, as well as high precision to build. The company aims to complete this version in 2025.

Fig. 1: Reducing the cell size. Cells become available at each word-line/bit-line intersection. Source: Bryon Moyer/Semiconductor Engineering

This new cell provides better per-layer cell capacity, but it still employs a vertical capacitor. So even though Samsung is working toward a 3D stacked DRAM in the 2030 timeframe, the 4F² architecture isn’t going to be what gets it there.

Ferroelectrics also have been the topic of research at the Korea Advanced Institute of Science and Technology (KAIST). A paper from the 2022 Nano Convergence conference[3] explored fluorite-structured hafnium oxide, whereas a 2024 paper from the VLSI symposium[4] looked at hafnium-zirconium oxides (HZO). In both cases, the interest lies in what’s called the morphotropic phase boundary (MPB), which separates two phases of the material — although which two phases depends on the material.

Laying the cap on its side
The primary effort by established memory producers involves trying to get away from the vertical capacitor. As it is, such a layer would be extremely thick, making for ineffective stacking. By laying that capacitor on its side, the layer becomes much thinner — and yet the cell expands horizontally. Samsung plans such an approach for its stacked version. It refers to the modified cell as being smaller than 4F², which is at first glance unintuitive given the size of the capacitor. But it’s not the cell itself that has that size, because that will be much bigger. By stacking them, you take the actual cell size and divide by the number of layers, resulting in a much smaller effective area efficiency.

Samsung has not disclosed exactly how it will achieve that. But Lam Research posted a blog illustrating ideas for how this could be done. Lam is a semiconductor processing equipment vendor, so presumably it isn’t getting into the DRAM business. The company also is unlikely to disclose what its customers are doing, so the following discussion is really more illustrative than definitive.

The first basic notion is to flip the cell, with the vertical cap, onto its side, bringing its own challenges. “Continuous scaling of DRAM technology is driving a move to 3D geometry using a stack of horizontal capacitors,” said Vincent. “The horizontal orientation necessitates lateral etching, which is difficult because recess sizes vary greatly.”

Fig. 2: Flipping a cell to make the capacitor horizontal. In this conceptual view, the drawing is literally rotated. But this, on its own, is not a manufacturable configuration. Source: Lam Research

Lam then proposes three changes to the cell. The first is to slide the bit line over to the other side of the cell, reducing the length of the active area along the way. At this point, the long thin caps look out of place. They have that shape because, when vertical, that has a beneficial effect on area. But once flipped, it hurts the area. It’s the surface area of the capacitor that matters, so now there’s room to make the cap wider and shorter.

“Capacitors need to be shortened — they can’t be as long as they are currently tall — and stacked to optimize the quantity of bits per unit area,” said Vincent. “A proper balance between the area per bit and the capacitor length needs to be defined by process/design optimization.”

Gate-all-around (GAA) transistors further shrink the die in Lam’s second proposed cell change. Others agree on the value of the GAA move.

“A more radically reimagined architecture for gate-all-around (GAA) inclusion and capacitor structure can make more sense from a functional standpoint,” said Brewer’s Soden. “But it will require new spin-on steps, lithography, and deposition/etch integration.”

Fig. 3: Making a smaller horizontal cell. The bit line can slide to the right side, making room for a wider — and hence shorter — capacitor that takes less area. Source: Lam Research

The final major change attaches multiple cells to each bit line for greater efficiency.

Fig. 4: Raising the number of cells attached to each bit line. Source: Lam Research

One of the more recognizable features of 3D NAND is the staircase on the sides employed for connections to the individual layers. While effective, it also takes a fair bit of space and effort. Lam instead proposes internal vias as connections.

Fig. 5: Internal vias serve to contact the layers as an alternative to a staircase structure. Source: Lam Research

This results in the stacked structure shown below in figure 6. The footprint of an individual cell is much larger than that of a 3D NAND cell, but no matter how that is realized, it’s much denser than traditional DRAM.

“Etch and deposition experts may be shocked at what our simulations propose,” cautioned Vincent. “For example, trenches with 30nm critical dimensions and 2µm depth are considered to be etched and filled in our architecture.” In other words, much work remains to turn these ideas into a commercially viable product.

Fig. 6: A 3D DRAM structure according to Lam’s proposals. Source: Lam Research

Doffing the cap
Any time a capacitor is involved in a DRAM cell, it’s going to require space in some direction.  Horizontally, it will be much larger than the 4F² that Samsung is pursuing for next year. It’s tempting, then, to ask if there are ways to do this without a capacitor, and indeed there are. Researchers have been looking at them for quite some time. But only one company has come forward with a commercial proposal rather than just a research project.

One alternative in research involves gate-controlled thyristors. A thyristor is a bipolar PNPN structure that, when triggered, latches up and conducts a high current. It can’t be shut off except by starving it of carriers, which takes a while. A gate-controlled version has an additional terminal that can shut it off more quickly.

The challenge with this approach is that it requires multiple word lines to set up the polarity of the various regions along a horizontal piece of silicon to create the PNPN structure. These aren’t copies of the same word line at the same voltage. Instead, they collectively act as a word line, but individually they will have differing voltages, with some positive and some negative to create enhancement or depletion regions. An earlier proposal required three such word lines, but further work by Macronix[5] reduced it to two.

Fig. 7: Controllable thyristor as a DRAM cell with no capacitor. Each “word line” actually has three lines at different voltages to set up the n and p regions. A two-word-line version was proposed by Macronix. Source: Bryon Moyer/Semiconductor Engineering

The other “capless” cell employs a floating body, which is similar to the floating gate used for flash. It’s a conducting region with no outlet, and as such it theoretically should be capable of holding charge. Such structures have been studied for a long time, particularly on silicon-on-insulator (SOI) wafers, but they’ve come up wanting.

Neo Semiconductor, however, claims to have overcome prior limitations and has proposed specific technology for commercial use. A second transistor gate at a negative voltage plus an ultra-thin body enables back-gate channel-depth (BCM) modulation to raise retention by 40,000X and the sensing window by 20X.

“Floating-body cells were developed 20 years ago, using an SOI wafer to isolate the cell body from the substrate in order to become a capacitor for electric charge storage,” explained Andy Hsu, CEO and co-founder of Neo Semiconductor. “However, it did not successfully enter mass production because of challenges related to data retention, leakage currents, and difficulty in controlling the floating body potential, especially when scaling down to smaller cell sizes. Based on simulations, this mechanism [dual gating] can increase the sensing margin and data retention.”

The floating body is a modestly sized structure as compared to the capacitors. It brings the cell size into the range used for NAND flash, although it’s still somewhat larger than a flash cell. Importantly, the read process is now non-destructive, which should reduce latency since post-read write-back would not be necessary. Read currents are about 10% that of a traditional cell.

Fig. 8: Neo’s 3D floating-body concept. The presence or absence of charge in the floating body determines the cell state. Source: Neo Semiconductor

This structure provides a DRAM stack-up that would look very similar to 3D NAND. “This technology is based on two mature technologies,” noted Hsu. “It combines floating-body cells and 3D NAND flash which already have been proven before,” although floating-body cells have never entered high-volume production, and the dual-gate version, which addresses prior floating-body issues, remains to be proven.

Fig. 9: Neo’s floating-body stacking structure. Source: Neo Semiconductor

Up until this year, the company used simulation to prove, at least on paper, that the new ideas worked. This year it released its TCAD simulation results and moved to start building proof-of-concept (PoC) wafers. “This first cell PoC will be at the cell level,” explained Hsu. “We can demonstrate the process, optimize the cell dimensions, and take measurements for all the operations.”

That first phase is expected to yield wafers in 2025. The second phase will integrate that module into a complete device, which is expected in 2026.

It’s always tough to sell the industry on completely new ideas. It’s even tougher when prior work has raised concerns about such techniques. Major memory makers will need to be thoroughly convinced that the ideas are solid before considering licensing. That’s the role of the PoCs. Given availability in 2026, the industry would still require time (often measured in years) to gain assurance that embarking in that direction won’t lead to last-minute fatal-flaw surprises.

The semiconductor business — especially the conservative memory industry — is replete with great ideas that were too revolutionary, losing to less-optimal-but-good-enough modifications to existing approaches. “New architectures are always more challenging than implementation of existing methodologies,” observed Soden.

For instance, if the Neo technology proves itself out, would Samsung abandon its horizontal-cap work? That, of course, depends on the promised benefit as traded off against the risk of a big departure from tradition.

In this case, the benefit is a significant cell-area reduction. Assuming it works, any manufacturer taking it up would have a cost or capacity benefit as compared with a company sticking with horizontal caps. The memory will still require refresh, but it may allow a slower refresh rate. That would save power. The PoC measurements should provide solid numbers that should help to determine future industry directions.

3D DRAM is not just around the corner
All efforts underway will require many years of development and evaluation before any of them achieves commercial traction. Lam’s proposals are just that. Someone else would need to run with them to develop a practical version. Samsung is focused first on its 4F² efforts before tackling stacking (at least according to its public statements). Thyristors are still in research, and Neo’s approach will need years of proving out.

It would be overly optimistic to expect much before the end of the decade. But based on current efforts, it appears likely that the world will end up with 3D monolithic stacked DRAM. The only question is what it will look like and when it will be ready.

References:

1. Moyer, “NAND Flash Targets 1,000 Layers,” Semiconductor Engineering, December 4, 2024, https://semiengineering.com/nand-flash-targets-1000-layers/.
2. Vincent, “3D DRAM Is Coming. Here’s a Possible Way to Build It,” July 14, 2023, https://newsroom.lamresearch.com/3D-DRAM-architecture-proposal.
3. Jung, et al., “A review on morphotropic phase boundary in fluorite-structure hafnia towards DRAM technology.” Nano Convergence 9, 44 (2022). https://doi.org/10.1186/s40580-022-00333-7
4. Gaddam et al., “Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology,” 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, DOI:10.1109/VLSITechnologyandCir46783.2024.10631348
5. C. Chen, et al., “Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL’s and Vertical BL for Better Cell Size Scaling and Array Selection,” Chen et al, Macronix, 2024 International Memory Workshop. DOI:10.1109/IMW59701.2024.10536917

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