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Blog Review: April 3

Cyber-physical threats; bare metal programming; reduced precision.

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Synopsys’ Taylor Armerding contends that as the IoT becomes more ubiquitous, the threat of cyber-physical attacks is rising, with the potential for a domino effect if even simple devices are compromised in large enough quantities.

Mentor’s Colin Walls considers the move away from programming on bare metal with the rise of drivers and RTOSes and when it makes sense to still use the old methods today.

Cadence’s Paul McLellan highlights a discussion with FBI Director Christopher Wray at RSA on the importance of private sector participation in tackling cyber threats and challenges the agency sees on the horizon.

A Rambus writer takes a look at reduced-precision computation, a method used in neural networks to reduce memory bandwidth demand and increase power efficiency.

Arm’s Hellen Norman explains the difference between the terms ‘machine learning’ and the more general ‘artificial intelligence’ plus a quick explainer of how machine learning works.

Intel’s David Hoffman says it’s time for stronger personal privacy laws in the US that put the burden for protecting personal information on regulators and the companies using that data.

Tibco’s Mike Alperin argues that blockchain could help alleviate some of the data sharing pain points in semiconductor manufacturing for better tracing and counterfeit reduction.

And don’t miss the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling warns that different starting points and definitions could have a big impact on autonomous vehicle design.

Technology Editor Brian Bailey asks how much would you pay for a model. Recently, the answer has been $$$.

OneSpin’s Sergio Marchese wonders if assertions enable engineers to design IP that are correct by construction.

Cadence’s Frank Schirrmeister explains why properly defining what digital twins are is an important part of determining their usefulness.

Synopsys’ Robert Ruiz talks about how greater complexity and smaller process nodes are driving a major shift in design-for-test implementation.

Silexica’s Maximilian Odendahl says tools can help address complex automotive software architectures efficiently.

Mentor’s Srinivas Velivala reveals a case study on improving DRC during base layers tapeout and managing IP interface DRC errors.

As DO-254 approaches its 19th birthday, Aldec’s Janusz Kitel proclaims it’s time to look beyond just using board-level testing.

eSilicon’s Mike Gianfagna shows off long-reach SerDes over a five-meter cable.

UltraSoC’s Jo Windel examines how the rapidly-growing embedded conference covers a range of sectors and application areas.



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