Dielectrics for 2D TMDs, Including Deposition Strategies And Emerging Dielectric Materials (Cambridge)


A new technical paper titled "Gate dielectrics for transistors based on two-dimensional transition metal dichalcogenide semiconductors" was published by researchers at University of Cambridge. "This perspective analyses the state of the art on 2D TMD and dielectric interfaces, highlighting key challenges in depositing oxide dielectrics on top of atomically thin TMD semiconductors. We provide... » read more

NVIDIA GPU Confidential Computing: Threat Model And Security Insights (IBM Research, Ohio State)


A new technical paper titled "NVIDIA GPU Confidential Computing Demystified" was published by IBM Research and Ohio State University. Abstract "GPU Confidential Computing (GPU-CC) was introduced as part of the NVIDIA Hopper Architecture, extending the trust boundary beyond traditional CPU-based confidential computing. This innovation enables GPUs to securely process AI workloads, providing ... » read more

Functional Hardware Trojans Specifically Tailored Tor SFQ (Univ. of Rochester)


A new technical paper titled "Hardware trojans in superconducting electronic circuits" was published by researchers at University of Rochester. Abstract "Hardware Trojans that exploit the unique characteristics of superconducting electronic (SCE) circuits are explored in this paper. Two types of hardware Trojan circuits are proposed: a magnetically-coupled data transmission Trojan embedded ... » read more

System-Level Approach To Reducing HBM Cost for AI inference (RPI, IBM)


A new technical paper titled "Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure" was published by researchers at Rensselaer Polytechnic Institute and IBM. Abstract "High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, pose... » read more

Detailed Study of Performance Modeling For LLM Implementations At Scale (imec)


A new technical paper titled "System-performance and cost modeling of Large Language Model training and inference" was published by researchers at imec. Abstract "Large language models (LLMs), based on transformer architectures, have revolutionized numerous domains within artificial intelligence, science, and engineering due to their exceptional scalability and adaptability. However, the ex... » read more

Chip Industry Technical Paper Roundup: July 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=445 /] Find more semiconductor research papers here. » read more

Research Bits: July 7


3D NAND PUF Researchers from Seoul National University developed a new hardware security technology based on commercially available 3D NAND flash memory. The approach is an adaptation of physical unclonable functions (PUFs) with the ability to hide a security key under user data when not in use and reveal it only when needed. The same memory space used for storing security keys can be repurpos... » read more

Accelerator Architecture For In-Memory Computation of CNN Inferences Using Racetrack Memory


A new technical paper titled "Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems" was published by researchers at National University of Singapore, A*STAR, Chinese Academy of Sciences, and Hong Kong University of Science and Technology. Abstract "Deep neural networks generate and process large volumes of data, posing challe... » read more

Development and Deployment of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel)


A new technical paper titled "System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution" was published by researchers at Intel Corporation. Abstract "The proliferation of chiplet-based designs, driven by the escalating computational demands of AI, presents unique validation challenges when integrating heterogenous chiplets. This paper investigat... » read more

Chip Industry Week in Review


[Editor's Note: Early edition due to the U.S. July 4th holiday.] The U.S. government lifted export restrictions that barred Synopsys, Siemens EDA, and Cadence from selling EDA tools to China. In a statement, Synopsys said it received a letter from the U.S. Commerce Department immediately rescinding those restrictions. Siemens issued a similar statement. Which tools or hardware accelerated t... » read more

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