Chip Failures: Prevention And Responses Over Time
By Ed Sperling - 19 Mar, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the causes of chip failures, how to respond to them, and how that can change over time, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, hi... » read more

Blog Review: Mar. 19
By Jesse Allen - 19 Mar, 2025 - Comments: 0

Cadence's Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests. Siemens EDA's Stephen V. Chavez examines the use of blind and buried vias in high-density i... » read more

Optimizing Data Movement In SoCs And Advanced Packages
By Ed Sperling - 18 Mar, 2025 - Comments: 0

The amount of data that needs to move around a chip is growing exponentially, driven by the rollout of AI and more sensors everywhere. There may be hundreds of IP blocks, more compute elements, and many more wires to contend with. Andy Nightingale, vice president of product management and marketing at Arteris, talks about the demand for low-latency on-chip communication in increasingly complex ... » read more

Research Bits: Mar. 18
By Jesse Allen - 18 Mar, 2025 - Comments: 0

High-frequency signal conversion Researchers from ETH Zurich developed a plasmonic modulator capable of converting electrical signals into optical signals with a frequency of over a terahertz. The modulator is a tiny nanostructure made up of various materials, including gold, and makes use of the interaction between light and free electrons within the gold. It converts signals directly, red... » read more

Changes In Motor Control
By Ed Sperling - 17 Mar, 2025 - Comments: 0

Motors are changing in fundamental ways, and you can actually hear the difference. Vacuums, air conditioners, and home appliances are getting quieter. They're also becoming more efficient, able to last longer on a single battery charge or drawing less energy from the grid, and they're becoming more secure. Steve Tateosian, senior vice president for Infineon's IoT, Compute & Wireless Busines... » read more

GPU Or ASIC For LLM Scale-Up?
By Geoff Tate - 17 Mar, 2025 - Comments: 1

The CEOs of OpenAI, Anthropic, and xAI share a strikingly similar vision — AI's progress is exponential, it will change humanity, and its impact will be greater than most people expect. This is more than just speculation. The market for AI, and its value, are real today: A human developer with GitHub CoPilot codes 55% faster with AI. GPT-4 scores 88th percentile on the LSAT vs. 50t... » read more

New Data Center Protocols Tackle AI
By Bryon Moyer - 17 Mar, 2025 - Comments: 0

Compute nodes in AI and HPC data centers increasingly need to reach out beyond the chip or package for additional resources to process growing workloads. They may commandeer other nodes in a rack (scale-up) or employ resources in other racks (scale-out). The problem is there currently is no open scale-up protocol. So far this task has been dominated by proprietary protocols, because much of ... » read more

Accelerating Digital Transformation With Tight Integration Of Manufacturing Data
By Jonathan Holt - 17 Mar, 2025 - Comments: 0

Many semiconductor companies are involved in digital transformation of their overall processes and operations. Manufacturing is one of the most critical and value generating processes in a semiconductor company. Being able to tightly integrate manufacturing with the rest of the enterprise is a critical element of a successful digital transformation program. Recognizing the value of real-time... » read more

Design Optimization Techniques To Improve NC-CFET Performance
By Technical Paper Link - 14 Mar, 2025 - Comments: 0

A new technical paper titled "Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configu... » read more

Chip Industry Week In Review
By The SE Staff - 14 Mar, 2025 - Comments: 0

ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

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