Facilitating Complex SoC Design Through Automation And Integration


The design demands of today’s highly advanced system-on-chip (SoC) devices have long outgrown the capabilities of manual workflows to manage them effectively. As these chips become more complex, only sophisticated, high-performance, and scalable automation can ensure that every component of the SoC functions seamlessly. The SoC integration challenge A fundamental aspect of SoC design is the... » read more

How To Streamline Your Advanced Package Interconnect Designs


Monolithic system-on-chip (SoC) designs was once a popular choice. However, they face significant constraints in the era of AI. By forcing all chip functions into a single die and process node, they reduce engineering, manufacturing, and design cost flexibility. In contrast, the multi-die nature of chiplets enables different SoC functions to be designed and verified independently and fabrica... » read more

Solving Clock Signal Integrity And Jitter Issues


A recent blog post discussed the challenges of clock signal integrity and clock jitter in deep submicron semiconductor devices. Nice, clean clock signals are degraded due to many factors, including noise in the power delivery network (PDN). Timing variation due to clock jitter is also a serious issue, especially for chips operating at low voltage with high frequencies. The impact due to cloc... » read more

From Standards To Systems: The Chiplet Era On Arm


For three decades, Arm didn’t just participate in industry transformation — it redefined it. From mobile to cloud to automotive, Arm’s architecture and the AMBA ecosystem have become the backbone of scalable compute. Now the industry faces its next structural shift: The era of monolithic SoCs is tapering and giving way to the era of chiplet systems. While complex SoCs are going to b... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets


Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

Energy-Efficient Liquid Cooling for Advanced Semiconductor Packaging (KAIST)


A new technical paper, "Highly energy-efficient manifold microchannel for cooling electronics with a coefficient of performance over 100,000," was published by researchers at KAIST. The study presents a CMOS-compatible manifold microchannel cooler that removes over 2,000 W/cm² using single-phase water at only 8 kPa pressure drop, achieving a record COP of 106,000—a significant improvement... » read more

Assuring Comprehensive Security Coverage In Hardware Design


Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs. By adopting a systematic framework and measuring coverage throughout the pre-silicon development cycle, you can proactively identify vulnerabilities and strengthen your hardware’s resilience. Downl... » read more

How Long Will CAN Stick Around As Rival Networks Speed Up?


Key Takeaways Automotive Ethernet is rapidly becoming the backbone of software-defined vehicles for higher bandwidth, scalability, and advanced features like TSN and security that legacy protocols cannot match. CAN, LIN, and other legacy networks will not disappear quickly because they are deeply embedded, low‑cost, and proven, but they are increasingly seen as inadequate for future A... » read more

Blog Review: Apr. 29


Synopsys' Madhumita Sanyal shows why interface IP has emerged as the keystone for building scalable, reliable 3D multi-die designs in which interconnects often have a greater influence on overall system capability than the peak performance of individual dies. Cadence's Frank Ferro checks out why SOCAMM2 built on LPDDR is being deployed in AI data centers, increasing memory bandwidth and capa... » read more

From Silos to Systems, from Data to Insight


The semiconductor industry is experiencing unprecedented growth in complexity, scale, and data volume. Engineering organizations are managing larger and longer-running projects, integrating more diverse methodologies, and relying on an expanding ecosystem of specialized tools. At the same time, they face increasing demands for compliance, traceability, security, and data sovereignty. In this en... » read more

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