Chip Industry Technical Paper Roundup: May 5
By Linda Christensen - 05 May, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design 🔗 Univ. of Edinburgh, Peking Univ., Cambridge, CAS, HKUST In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Direct... » read more

Research Bits: May 5
By Jesse Allen - 05 May, 2026 - Comments: 0

AI power prediction Researchers from MIT and the MIT-IBM Watson AI Lab developed a prediction tool that can quickly tell data center operators how much power will be consumed by running a particular AI workload on a certain processor or AI accelerator chip. It can be applied to a wide range of hardware configurations. The lightweight estimation model captures the power usage pattern of a GP... » read more

Designing Chips In The Context Of Rapidly Evolving AI
By Ann Mutschler - 04 May, 2026 - Comments: 0

Key Takeaways: Agentic edge AI drives long-lived, tool-mediated loops with variable demands for compute, tokens, and memory. Edge PPA is dominated by memory hierarchy and data movement, forcing tight feature triage and robust RAS. Rapid model churn (multimodal, MoE, new formats) requires programmable, headroom-rich compute, interconnect, and runtime. Experts At The Table: Ch... » read more

From Simulation Checkpoints To Continuous Physics
By Satish Radhakrishnan - 04 May, 2026 - Comments: 0

Semiconductor engineering teams have long relied on an iterative simulation workflow: define the scenario, prepare the model, run the analysis, review the results, adjust the design, and repeat until a decision can be made. That workflow remains essential. Simulation is still one of the primary ways teams evaluate physical behavior before hardware is built. But as chips, packages, and system... » read more

Potential Route To Photonic FPCA Using NV Low-Loss Phase Change Material (Oxford)
By Technical Paper Link - 02 May, 2026 - Comments: 0

A new technical paper, "Nonvolatile photonic field-programmable coupler array," was published by researchers at University of Oxford. Abstract "Programmable photonic networks carry out universal unitary functions by independently operating on the amplitude and phase of guided light. Exploiting the reconfigurability and spatiospectral degrees of freedom of these systems, the majority of stat... » read more

Chip Industry Week in Review
By The SE Staff - 01 May, 2026 - Comments: 0

Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

Transforming DRC Closure At Advanced Nodes
By James Paris - 30 Apr, 2026 - Comments: 0

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

Creating Agentic EDA Methodologies
By Brian Bailey - 30 Apr, 2026 - Comments: 1

Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
By Ann Mutschler - 30 Apr, 2026 - Comments: 0

Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

Unlocking High-Speed Serial Link Signal Integrity With AMI Model
By Priyadarshini N D - 30 Apr, 2026 - Comments: 0

As the demand for faster data rates in high-speed interfaces such as PCIe, USB, and DDR continues to escalate, maintaining signal integrity has become a significant challenge for engineers. Traditional SPICE-based simulations, while precise, often suffer from computational intensity, making it impractical to model the intricate behavior of high-speed signals across millions of bits. This is ... » read more

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