3D-stacked near-memory LLM decoding; In-SoIC ESD protection for chiplets; thermal management for adv. packaging; quantum circuits on chiplets; agentic AI for formal verification; multilayer nanostructure characterization; liquid cooling for adv. packages; NV photonic coupler arrays.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design 🔗 | Univ. of Edinburgh, Peking Univ., Cambridge, CAS, HKUST |
| In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions 🔗 | UC Riverside |
| Epoxy Composites Reinforced with Long Al2O3 Nanowires for Enhanced Thermal Management in Advanced Semiconductor Packaging 🔗 | Georgia Tech, NCKU |
| Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures 🔗 | TU Munich |
| Agentic AI-based Coverage Closure for Formal Verification 🔗 | Infineon, NIT Jalandhar |
| Characterisation of Complex Multilayer Nanostructures with High Aspect Ratio 🔗 | Aalto Univ., Univ. of Eastern Finland, Chipmetrics OY, VTT MIKES |
| Highly energy-efficient manifold microchannel for cooling electronics with a coefficient of performance over 100,000 🔗 | KAIST |
| Nonvolatile photonic field-programmable coupler array 🔗 | Univ. of Oxford |
Find more semiconductor research papers here.
Leave a Reply