Chip Industry Technical Paper Roundup: May 5


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design 🔗 Univ. of Edinburgh, Peking Univ., Cambridge, CAS, HKUST In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Direct... » read more

Leveraging Agentic AI Techniques to Improve Formal Verification (Infineon, et al.)


A new technical paper, "Agentic AI-based Coverage Closure for Formal Verification," was published by researchers at Infineon and the NIT Jalandhar. Abstract "Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines.... » read more