Chip Industry Technical Paper Roundup: May 5


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design 🔗 Univ. of Edinburgh, Peking Univ., Cambridge, CAS, HKUST In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Direct... » read more

Reflectometry-Based Technique for Characterising Complex Thin-Film Structures (Aalto U. et al.)


A new technical paper, "Characterisation of Complex Multilayer Nanostructures with High Aspect Ratio," was recent published by researchers at Aalto University, University of Eastern Finland, Chipmetrics OY, and VTT MIKES. Abstract "Deposition studies of deep vertical dips on semiconductor wafers can create problems at an industrial manufacturing scale, since cross-sectioning requires a lo... » read more