Controlled Shared Memory For Dynamically Controlling Data Communication Via Shared Memory Approaches (ASU, Intel)


A new technical paper titled "Controlled Shared Memory (COSM) Isolation: Design and Testbed Evaluation" was published by researchers at Arizona State University and Intel Corporation. Abstract "Recent memory sharing approaches, e.g., based on the Compute Express Link (CXL) standard, allow the flexible high-speed sharing of data (i.e., data communication) among multiple hosts. In information... » read more

A Survey Of Digital Twins and Other Prototyping Technologies for Vehicles


A new technical paper titled "Digital Twin Technologies for Vehicular Prototyping: A Survey" was published by researchers at Central Michigan University and University of Florida. Abstract "Digital Twin (DT) technology is widely regarded as one of the most promising tools for industry development, demonstrating substantial application across numerous cyber-physical systems. Gradually, this ... » read more

Impact Of Cryogenic Temps On The Minimum-Operating Voltage Of 5nm FinFETs-Based SRAM (IIT, UC Berkeley et al)


A new technical paper titled "An Investigation of Minimum Supply Voltage of 5nm SRAM from 300K down to 10K" was published by researchers at Indian Institute of Technology, UC Berkeley and Munich Institute of Robotics and Machine Intelligence. Abstract "In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm ... » read more

Differences In The Lithographic Impact Of Particles On The Pellicle Surface Depending On Type Of EUV Mask Pattern


A new technical paper titled "Impact of Sn Particle-Induced Mask Diffraction on EUV Lithography Performance Across Different Pattern Types" was published by Hanyang University and Paul Scherrer Institute. Abstract "This study investigates the differences in the lithographic impact of particles on the pellicle surface depending on the type of extreme ultraviolet (EUV) mask pattern. Using a... » read more

Chip Industry Week in Review


To listen to the podcast version, click here. TSMC unveiled an unusually detailed roadmap at this week's North America Technology Symposium, including future architectures for 3D-ICs for high-performance computing and small, extremely low-power chips for AR/VR glasses, and two implementations of system-on-wafer. Fig. 1: TSMC's future packaging and stacking roadmap. Source: TSMC The ... » read more

Data Movement Is the Energy Bottleneck of Today’s SoCs


In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). The efficiency of data movement across the chip has become just as important. Whether designed for data centers or edge AI devices, SoCs must now prioritize data transport as a core architectural consideration. Moving data efficiently across the silicon f... » read more

Tape-Out Failures Are The Tip Of The Iceberg


The headline numbers for the new Wilson Research/Siemens functional verification survey are out, and it shows a dramatic decline in the number of designs that are functionally correct and manufacturable. In the past year, that has dropped from 24% to just 14%. Along with that, there is a dramatic increase in the number of designs that are behind schedule, increasing from 67% to 75%. Over the ne... » read more

AI Drives Re-Engineering Of Nearly Everything In Chips


AI's ability to mine patterns across massive quantities of data is causing fundamental changes in how chips are used, how they are designed, and how they are packaged and built. These shifts are especially apparent in high-performance AI architectures being used inside of large data centers, where chiplets are being deployed to process, move, and store massive amounts of data. But they also ... » read more

AI-Driven Verification Regression Management


By Paul Carzola and Taruna Reddy Coping with the endless growth in chip size and complexity requires innovative electronic design automation (EDA) solutions at every stage of the development process. Better algorithms, increased parallelism, higher levels of abstraction, execution on graphics processing units (GPUs), and use of AI and machine learning (ML) all contribute to these solutions. ... » read more

Reap Rewards With Shift-Left Pattern Matching For Custom And AMS Designs


To keep up with the growing complexities of IC design, major semiconductor companies are adopting shift-left strategies. For verification, this means pulling much of the work into the physical design stage. By moving critical checks earlier in the design cycle, you can identify and resolve issues before they escalate, streamlining the overall development process. The Calibre tools have been ... » read more

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