Strain Engineering in 2D FETs (UCSB)
By Technical Paper Link - 07 Oct, 2024 - Comments: 0

A new technical paper titled "Strain engineering in 2D FETs: Physics, status, and prospects" was published by researchers at UC Santa Barbara. "In this work, we explore the physics and evaluate the merits of strain engineering in two-dimensional van der Waals semiconductor-based FETs (field-effect-transistors) using DFT (density functional theory) to determine the modulation of the channel m... » read more

TFETs: Design and Operation, Including Material Selection and Simulation Methods
By Technical Paper Link - 07 Oct, 2024 - Comments: 0

A new technical paper titled "Multiscale Simulation and Machine Learning Facilitated Design of Two-Dimensional Nanomaterials-Based Tunnel Field-Effect Transistors: A Review" was published by researchers at University of Chicago and Argonne National Lab. Abstract "Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transi... » read more

Government Chip Funding Spreads Globally
By Liz Allan - 07 Oct, 2024 - Comments: 0

This is the first in a series of articles tracking government chip investments. See part two for Americas-focused funding and part three for the UK and EMEA. Countries around the world are ramping up investments into their semiconductor industries as part of new or existing approaches. The increased government activity stems from growing awareness of the strategic importance of the chip sect... » read more

Multi-Node, Virtualized Neuromorphic Architecture
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new technical paper titled "NeuroVM: Dynamic Neuromorphic Hardware Virtualization" was published by researchers at Stanford University, UT Austin and Temsa Research & Development Center. Abstract "This paper introduces a novel approach in neuromorphic computing, integrating heterogeneous hardware nodes into a unified, massively parallel architecture. Our system transcends traditional ... » read more

Rowhammer Protection By Addressing Root Cause (Georgia Tech)
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new technical paper titled "Preventing Rowhammer Exploits via Low-Cost Domain-Aware Memory Allocation" was published by researchers at Georgia Tech. Abstract "Rowhammer is a hardware security vulnerability at the heart of every system with modern DRAM-based memory. Despite its discovery a decade ago, comprehensive defenses remain elusive, while the probability of successful attacks grows ... » read more

Review Paper: Challenges Required To Bring the Energy Consumption Down in Microelectronics (Rice, UC Berkeley, Georgia Tech, Et al.)
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new review article titled "Roadmap on low-power electronics" by researchers at Rice University, UC Berkeley, Georgia Tech, TSMC, Intel, Harvard, et al. This roadmap to energy efficient electronics written by numerous collaborators covers materials, modeling, architectures, manufacturing, metrology and more. Find the technical paper here. September 2024. Ramamoorthy Ramesh, Sayeef Sal... » read more

Gold Substrate Plays Boosts Performance of Tellurium-Based Memristors
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new technical paper titled "Non-Volatile Resistive Switching in Nanoscaled Elemental Tellurium by Vapor Transport Deposition on Gold" was published by researchers at Politecnico di Milano, UT Austin, and STMicroelectronics. Abstract: "Two-dimensional (2D) materials are promising for resistive switching in neuromorphic and in-memory computing, as their atomic thickness substantially impr... » read more

Ambipolar Schottky-based FeFET For Ultrascaled Memory Applications
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new technical paper titled "On the Potential of Ambipolar Schottky-Based Ferroelectric Transistor Designs for Enhanced Memory Windows in Scaled Devices" was published by researchers at Global TCAD Solutions, Igor Sikorsky Kyiv Polytechnic Institute, INSA Lyon, and NaMLab. "Here, we promote an ambipolar Schottky-based ferroelectric transistor (AS-FeFET) as an alternative design. We demonstr... » read more

Chip Industry Week In Review
By The SE Staff - 04 Oct, 2024 - Comments: 0

Amkor will provide turnkey advanced packaging and test services to TSMC in Amkor's planned facility in Peoria, Arizona, in a deal announced on Thursday. The companies jointly specified the packaging technologies, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS). President Biden signed into law a bill that exempts some semiconductor projects funded by the U.S.... » read more

Partitioning In The Chiplet Era
By Ann Mutschler - 03 Oct, 2024 - Comments: 0

The widespread adoption of chiplets in domain-specific applications is creating a partitioning challenge that is much more complex than anything chip design teams have dealt with in previous designs. Nearly all the major systems companies, packaging houses, IDMs, and foundries have focused on chiplets as the best path forward to improve performance and reduce power. Signal paths can be short... » read more

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