New Innovative Way To Functionally Verify Heterogeneous 2D/3D Package Connectivity
By Siemens EDA - 12 Mar, 2025 - Comments: 0

Historically, IC package design has been a relatively simple task which allowed the die bumps to be fanned out to a geometry suitable for connecting to a printed circuit board. The package netlist was often captured by the package designer, typically using Excel to manually assign net names to the desired die bumps and BGA balls to achieve the intended connection. Modern package and interpos... » read more

Silicon Reimagined: New Foundations For The Age of AI
By Arm - 12 Mar, 2025 - Comments: 0

The semiconductor industry is undergoing a pivotal transformation driven by the rise of artificial intelligence (AI) and the slowing of traditional Moore’s Law scaling.  In this comprehensive 42 page report, several key trends shaping the industry’s future are highlighted. The push toward more specialized architectures tailored for specific workloads, particularly in AI. The critic... » read more

Application Of External CFD Modeling In Data Center Design
By Cadence - 12 Mar, 2025 - Comments: 0

Rising IT densities and AI workloads demand smarter heat management and equipment placement. This paper "Application of External CFD Modeling in Data Center Design" explores how external computational fluid dynamics (CFD) modeling provides crucial insights by resolving airflow patterns around buildings. Why Choose External CFD Modeling? Recommended by The Green Grid, it helps predict: ... » read more

Unlocking Generative AI On The Edge Across The Semiconductor Value Chain
By Expedera - 12 Mar, 2025 - Comments: 0

In the second of a three-part series, Expedera, in conjunction with the Global Semiconductor Alliance’s Emerging Technologies (EmTech) group, explores “Unlocking Generative AI on the Edge across the Semiconductor Value Chain”. Included in this white paper is an examination of how members of the value chain (including IP providers, EDA vendors, fabless chip makers, foundries, OSATs, OEMs, ... » read more

LLE-Aware Design Methodology To Avoid Timing And Power Pessimism
By Synopsys - 12 Mar, 2025 - Comments: 0

As chips move to ever-finer geometries, the active region (diffusion) shapes of neighboring cells can impact timing analysis and power calculations for the entire design. The LLE (Local Layout Effect) impact must be measured, but the impact is reflected very conservatively using conventional approaches. This paper describes a LLE-aware design methodology that mitigates the conservatism of co... » read more

Extracting Parasitic Impedance Of Semiconductor Power Modules
By Ansys - 12 Mar, 2025 - Comments: 0

As a key component in energy conversion system, power semiconductor devices are widely used in various applications, e.g., electric vehicles, renewable energy conversion, and uninterrupted power supplies. The trend for power converter design is always toward higher power density. Power modules that integrate multiple semiconductor devices can meet this demand. It also reduces the compl... » read more

Blog Review: Mar. 12
By Jesse Allen - 12 Mar, 2025 - Comments: 0

Cadence's P. Saisrinivas explains the relationship between drive strength and cell delay and why it is key to choose the appropriate drive strength to meet timing constraints while minimizing power and area. Siemens' Daniel Berger and Dirk Hartmann tackle the readout problem of accurately measuring the state of a quantum system after it has undergone a quantum computation, which becomes incr... » read more

A Novel Tier Partitioning Method in 3DIC Placement Optimizing PPA
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation" was published by researchers at Seoul National University and Ulsan National Institute of Science and Technology. Abstract "3D ICs are renowned for their potential to enable high-performance and low-power designs by utilizing denser and shorter inter-tier connections. In the physical design f... » read more

Thermal-Aware DSE Framework for 3DICs, With Advanced Cooling Models
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs" was published by researchers at University of Michigan, Shanghai Jiao Tong University and University of Virginia. Abstract "The rapid advancement of three-dimensional integrated circuits (3DICs) has heightened the need for early-phase design spa... » read more

Measuring Multi-Layer Ultra-Thin Critical Films
By Jiangtao Hu - 11 Mar, 2025 - Comments: 0

Artificial intelligence is one of the driving forces in today’s semiconductor industry, with more traditional market drivers like high performance compute and smart phones continuing to play important roles. This situation is unlikely change in the years ahead as chip makers continue their quest to create the most advanced nodes. With 3nm nodes in production and 2nm nodes on the horizon, the ... » read more

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