Emulation-based SoC Security Verification (U. of Florida)
By Technical Paper Link - 17 Apr, 2026 - Comments: 0

A new technical paper, "Emulation-based System-on-Chip Security Verification: Challenges and Opportunities," was published by researchers at University of Florida. Abstract "Increasing system-on-chip (SoC) heterogeneity, deep hardware/software integration, and the proliferation of third-party intellectual property (IP) have brought security validation to the forefront of semiconductor desig... » read more

Chip Industry Week In Review
By The SE Staff - 17 Apr, 2026 - Comments: 0

Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Chiplet Standards Aim For Plug-n-Play
By Bryon Moyer - 16 Apr, 2026 - Comments: 0

Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

Silicon Photonics Lights The Way To More Efficient Data Centers
By Katherine Derbyshire - 16 Apr, 2026 - Comments: 0

Key Takeaways Photonic interconnects potentially increase bandwidth density while significantly reducing power consumption. AI workloads are driving their adoption in data centers. On the other hand, photonic interconnects require a variety of different materials, introducing process compatibility and thermal and mechanical stress issues. Integrated electro-optical I/O modules are th... » read more

eBeam Initiative At SPIE ALP 2026: Continuing Progress On Curvilinear, EUV, And Data Challenges
By Jan Willis - 16 Apr, 2026 - Comments: 0

The eBeam Initiative’s annual lunch at SPIE Advanced Lithography and Patterning has long served as a focal point for eBeam technology education for the industry. This year marked our 17th gathering, with approximately 150 attendees joining us. As in past years, the value of the session was less about any single topic and more about the collective signal across different parts of the ecosystem... » read more

Breakthrough Thin GaN Chiplet Technology
By Han Wui Then - 16 Apr, 2026 - Comments: 0

Researchers at Intel Foundry have demonstrated a gallium nitride (GaN) chiplet technology built on 300 mm GaN-on-silicon wafers, marking a significant leap forward in semiconductor design. Presented at the 2025 IEEE International Electron Devices Meeting (IEDM), this work tackles one of the most pressing challenges in modern computing: how to deliver more power, speed, and efficiency in an incr... » read more

Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication
By Swapnil Kailash More - 16 Apr, 2026 - Comments: 0

By Swapnil Kailash More and Roopa Hegde As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advan... » read more

Meeting High-Frequency And Power Density Challenges With Flip Chip MLF Packaging
By KyungSu Kim - 16 Apr, 2026 - Comments: 0

The relentless march of semiconductor scaling continues to reshape the packaging landscape, driven by Moore’s Law and the demand for higher performance in increasingly compact form factors [1]. Over the past two decades transistor density has increased exponentially, with leading-edge processes now achieving densities exceeding 100 million transistors per square millimeter. Certain applica... » read more

Automate And Speed Up TCAD Calibration With Expert Modules And ML Calibration Accelerator
By Saurabh Suryavanshi - 16 Apr, 2026 - Comments: 0

Increasing complexity in semiconductor manufacturing has pushed the time to market and R&D costs significantly higher. In the world of AI, there is increased focus on efficiency to help address these issues simultaneously. Wafer-based learning, which is an iterative and linear process, is a key contributor to the increased semiconductor development time and cost. Technology computer-aided d... » read more

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