GPU Or ASIC For LLM Scale-Up?


The CEOs of OpenAI, Anthropic, and xAI share a strikingly similar vision — AI's progress is exponential, it will change humanity, and its impact will be greater than most people expect. This is more than just speculation. The market for AI, and its value, are real today: A human developer with GitHub CoPilot codes 55% faster with AI. GPT-4 scores 88th percentile on the LSAT vs. 50t... » read more

New Data Center Protocols Tackle AI


Compute nodes in AI and HPC data centers increasingly need to reach out beyond the chip or package for additional resources to process growing workloads. They may commandeer other nodes in a rack (scale-up) or employ resources in other racks (scale-out). The problem is there currently is no open scale-up protocol. So far this task has been dominated by proprietary protocols, because much of ... » read more

Accelerating Digital Transformation With Tight Integration Of Manufacturing Data


Many semiconductor companies are involved in digital transformation of their overall processes and operations. Manufacturing is one of the most critical and value generating processes in a semiconductor company. Being able to tightly integrate manufacturing with the rest of the enterprise is a critical element of a successful digital transformation program. Recognizing the value of real-time... » read more

Design Optimization Techniques To Improve NC-CFET Performance


A new technical paper titled "Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configu... » read more

Chip Industry Week In Review


ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Reducing Voltage Guard Band


The 2025 International Solid State Circuits Conference was held in San Francisco from February 16th to 20th. IBM presented three papers[1,2,3] based on their Samsung 5nm Tellum II chip. These are interesting in terms of the technology and the specifics about the design and measures taken to improve energy efficiency and reduce power. My first remembrance of a company specializing in guard-ba... » read more

Easier Assertion Development And Debug With Simulation Replay


By Vin Liao and Robert Ruiz Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of design intent, specifying how the design should behave—and not behave—under specified conditions. They range from simple statements, for example, that a multi-bit... » read more

Enabling Next-Generation Automotive Zonal Architecture With MIPI


The evolution of automotive architecture has followed three key stages: distributed architecture, domain-centralized architecture, and emerging zonal architecture. Each stage reflects advancements in functionality, complexity, and efficiency. Distributed architecture, prevalent in early vehicles, relied on numerous function-specific Electronic Control Units (ECUs). While effective for modularit... » read more

Fulfilling 3D-IC Trade-Off Analyses (And Benefits) With An AI Assist


As we walk around with supercomputers in our pockets and work at desks on even more powerful supercomputers, a lot of processing has moved to the cloud. As a politician described, this can be problematic on a day when there are no clouds in the sky. The world discovered the truth of those words when Crowdstrike struck on July 19, 2024. System designers who spent years balancing power, performan... » read more

Static Timing Analysis: Cell Delay Vs. Cell Drive Strength


Have you ever wondered how a predator succeeds or its prey escapes in the jungle? It’s the breathtaking speed and agility of the predator (say, a leopard) as it chases prey (say, a deer). The VLSI circuit operation is very similar. If the driving cell is strong, it takes less delay and changes the output quicker than a weaker driver, which produces a sluggish response and takes longer t... » read more

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