Chip Architectures Becoming Much More Complex With Chiplets


The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

Gold In The Machine: Scaling Infrastructure For The Age Of AI


During the gold rush, hopeful prospectors flooded the west to make their fortunes in gold. Today, technology pioneers are looking to stake their claim in the realm of artificial intelligence (AI). Price Waterhouse Cooper (PWC) estimates that 45% of total global economic gains by 2030 will be driven by AI as more sectors embrace the productivity and product enhancement benefits of AI. PWC’s ... » read more

AI Infrastructure At A Crossroads


By Ramin Farjadrad and Syrus Ziai There is a big push to achieve greater scale, performance and sustainability to fuel the AI revolution. More speed, more memory bandwidth, less power — these are the holy grails. Naturally, the one-two punch of StarGate and DeepSeek last week has raised many questions in our ecosystem and with our various stakeholders. Can DeepSeek be real? And if so, w... » read more

Chiplets Still A Challenge With UCIe 2.0


Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires. Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable s... » read more

Design Customization Puts Heavy Burden On Verification


Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor Engineering sat down with a panel of experts, including Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group director for verification software product management at Cad... » read more

Fast Monte Carlo Simulations For Timing Variation Analysis


Process variations and device mismatches profoundly affect the latest ultra-small geometrical processes. Complexity creates additional factors that impact device manufacturing variability, which in turn impact overall yield. Monte Carlo (MC) simulations use repeated random sampling to relate process variations to circuit performance and functionality, thus determining how they impact yield. How... » read more

Apple CPU Attacks: SLAP and FLOP (Georgia Tech, Ruhr University Bochum)


Two technical papers were published by researchers at Georgia Tech and Ruhr University Bochum detailing CPU side-channel attack vulnerabilities on Apple devices that could reveal confidential data. FLOP: Breaking the Apple M3 CPU via False Load Output Predictions"  Authors: Jason Kim, Jalen Chuang, Daniel Genkin and Yuval Yarom 2025. "We present FLOP, another speculative execution att... » read more

Ultranarrow Semiconductor WS2 Nanoribbon FETs (Chalmers)


A new technical paper titled "Ultranarrow Semiconductor WS2 Nanoribbon Field-Effect Transistors" was published by researchers at Chalmers University of Technology. Abstract "Semiconducting transition metal dichalcogenides (TMDs) have attracted significant attention for their potential to develop high-performance, energy-efficient, and nanoscale electronic devices. Despite notable advancem... » read more

Topology And Connection Architecture Of CXL Pooling Systems (Microsoft, Columbia)


A new technical paper titled "Octopus: Scalable Low-Cost CXL Memory Pooling" was published by researchers at University of Washington, Microsoft Azure and Columbia University. Abstract "Compute Express Link (CXL) is widely-supported interconnect standard that promises to enable memory disaggregation in data centers. CXL allows for memory pooling, which can be used to create a shared memory ... » read more

Controlling Speckle Contrast Using Existing Lithographic Scanner Knobs to Understand LWR (Samsung, ASML)


A new technical paper titled "Controlling Speckle Contrast Using Existing Lithographic Scanner Knobs to Explore the Impact on Line Width Roughness" was published by researchers at Samsung, ASML and Sungkyunkwan University. Abstract "Local critical dimension uniformity (LCDU) or line width roughness (LWR) is increasingly important in argon fluoride (ArF) immersion lithography systems (scanne... » read more

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