Optimizing Wafer Edge Processes For Chip Stacking

By Laura Peters - 23 Sep, 2024 - Comments: 0

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

Chip Industry Week In Review

By The SE Staff - 20 Sep, 2024 - Comments: 0

Synopsys agreed to sell its Optical Solutions Group to Keysight for an undisclosed amount, in a deal deemed necessary for Synopsys to win regulatory approval for its planned acquisition of Ansys. The sale to Keysight is contingent on the Synopsys-Ansys deal going through. Meanwhile, Ansys has its own optical business. The U.S. Department of Defense (DoD) made the first awards for Microelectr... » read more

Improving The Air-Stability and NBTI Reliability of BEOL CNFETs

By Technical Paper Link - 19 Sep, 2024 - Comments: 0

A new technical paper titled "Overcoming Ambient Drift and Negative-Bias Temperature Instability in Foundry Carbon Nanotube Transistors" was published by researchers at MIT, Stanford University, Carnegie Mellon University and Analog Devices. Abstract: "Back-end-of-line (BEOL) logic integration is emerging as a complementary scaling path to supplement front-end-of-line (FEOL) Silicon. Among ... » read more

Mixed Signal In-Memory Computing With Massively Parallel Gradient Calculations of High-Degree Polynomials

By Technical Paper Link - 19 Sep, 2024 - Comments: 0

A new technical paper titled "Computing high-degree polynomial gradients in memory" was published by researchers at UCSB, HP Labs, Forschungszentrum Juelich GmbH, and RWTH Aachen University. Abstract "Specialized function gradient computing hardware could greatly improve the performance of state-of-the-art optimization algorithms. Prior work on such hardware, performed in the context of Isi... » read more

Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications

By InRak Kim - 19 Sep, 2024 - Comments: 0

The conventional flip chip ball grid array (FCBGA) package platform has wide industry usage and provides high electrical performance. However, as high performance requirements increased, it encounters significant challenges. FCBGA packages frequently encounter underfill cracks after long term reliability or harsh reliability test conditions for automotive devices. Figure 1 shows the typical und... » read more

Reducing Transistor Capacitance At The 5nm Node Using A Source/Drain Contact Recess

By Pradeep Nanja - 19 Sep, 2024 - Comments: 0

In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One potential way to reduce this parasitic capacitance is to add a source/drain contact (CT) recess step when building the source/drain metal structure. However, this additional structure can potentially increase the source/drain to via resistance. Using... » read more

Legacy Process Nodes Are Critical To Many Industries

By David Park - 19 Sep, 2024 - Comments: 0

As the semiconductor industry continues to push the boundaries of innovation with advanced nodes, it is easy to overlook the critical role that ICs manufactured at legacy process nodes play in our everyday lives. While the spotlight often shines on the leading-edge advancements of 5nm technology and below, it’s the mature nodes, those above 28nm and even above 130nm, that are the unsung ch... » read more

Semiconductor Photomask Market Poised For Another Year Of Growth

By Jan Willis - 19 Sep, 2024 - Comments: 0

The semiconductor photomask market, a crucial component in chip manufacturing, is on track for another year of robust growth. This growth trajectory is supported by a series of technological advancements and market trends that continue to drive innovation in the industry. As the annual SPIE Photomask Technology Conference approaches in early October in Monterey, California, it presents an oppor... » read more

How Die Dimensions Challenge Assembly Processes

By Anne Meixner - 19 Sep, 2024 - Comments: 1

Multi-die assemblies are becoming more common and more complex due to technology advancements and market demands, but differing die dimensions are making this process increasingly challenging. To fully enable a multi-chiplet ecosystem, standardized component handling and interfaces are needed. The underlying concept is similar to LEGO blocks that simply snap together, yet it's nowhere near t... » read more

New Materials Are in High Demand

By Bryon Moyer - 19 Sep, 2024 - Comments: 0

Materials suppliers are responding to the intense pressures to improve power, performance, scaling, and cost issues, which follows a long timeline from synthesis to development and high volume manufacturing in fabs. The advances in machine learning help present a wide field of candidates, which engineers then narrow to potential use. When building standard logic semiconductor chips, the prim... » read more

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