Physically Aware NoCs
By Ed Sperling - 06 Mar, 2023 - Comments: 0

More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product m... » read more

Chip Industry’s Technical Paper Roundup: Mar. 6
By Linda Christensen - 06 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=84 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Research Bits: March 6
By Jesse Allen - 06 Mar, 2023 - Comments: 0

2D TMDs on silicon Engineers at MIT, University of Texas at Dallas, Institute for Basic Science, Sungkyunkwan University, Washington University in St. Louis, University of California at Riverside, ISAC Research, and Yonsei University found a way to grow 2D materials on industry-standard silicon wafers while preserving their crystalline form. Using a new “nonepitaxial, single-crystalline g... » read more

CXL-Based Memory Pooling System Meets Cloud Performance Goals And Significantly Reduces DRAM Cost
By Technical Paper Link - 05 Mar, 2023 - Comments: 0

A technical paper titled "Pond: CXL-Based Memory Pooling Systems for Cloud Platforms" was published by researchers at Virginia Tech, Intel, Microsoft Azure, Google, and Stone Co. Abstract "Public cloud providers seek to meet stringent performance requirements and low hardware cost. A key driver of performance and cost is main memory. Memory pooling promises to improve DRAM utilization and t... » read more

Printed Electronics: Direct Flipchip Bonding of Ultra-Thin Chip On A Recently-Developed Stretchable Substrate
By Technical Paper Link - 05 Mar, 2023 - Comments: 0

A new technical paper titled "Flip chip bonding on stretchable printed substrates; the effects of stretchable material and chip encapsulation" was published by researchers at Silicon Austria Labs and Institute for Smart Systems Technologies. Abstract "Stretchable printed electronics have recently opened up new opportunities and applications, including soft robotics, electronic skins, human-... » read more

Using Formal Verification To Optimize HLS-Produced Circuits (ETH Zurich)
By Technical Paper Link - 05 Mar, 2023 - Comments: 0

A new technical paper titled "Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking" was published by researchers at ETH Zurich. Abstract "Recent HLS efforts explore the generation of dynamically scheduled, dataflow circuits from high-level code; their ability to adapt the schedule at runtime to particular data and control outcomes promises superior performance to standar... » read more

Ternary LIM Operation of the TNAND and TNOR Universal Gates Using DG Feedback FETs
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "Logic-in-Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double-Gated Feedback Field-Effect Transistors" was published by researchers at Korea University. Abstract "In this study, the logic-in-memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double-gated feedback field-effect transistors. The component transistor... » read more

Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was written (preprint) by researchers at UC San Diego, UT Austin, and Purdue University. Abstract "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as implemented by the Intel Optane... » read more

Fast Parallel Multi-HDL Compiler (UC Santa Cruz)
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "A Multi-threaded Fast Hardware Compiler for HDL" was published by researchers at UC Santa Cruz. Abstract: "A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer’s productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in com... » read more

Energy-Efficient Execution Scheme For Dynamic Neural Networks on Heterogeneous MPSoCs
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs" was published (preprint) by researchers at LAMIH/UMR CNRS, Universite Polytechnique Hauts-de-France and UC Irvine. Abstract "Heterogeneous MPSoCs comprise diverse processing units of varying compute capabilities. To date, the mapping strategies of neural networks (NNs) onto ... » read more

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